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The efficiency of the “Siconi®” process, which is based on the use of a NH3 / NF3 remote plasma and anneals at temperatures less than 180°C, was recently assessed on SiGe surfaces. Siconi® removed GeO2 and SiO2, but was less efficient on GeOx. The presence of residual GeOx after a Siconi® process was minimized with the use, beforehand, of a wet oxidation. It consisted on dips in Standard Cleaning 1 (SC1) solutions made of NH4OH, H2O2 and H2O or in water with a few ppm of Ozone. A SiO2 - rich oxide was generated, then (P.E. Raynal et al, Microelec. Eng. 187-188, 84 (2018)). In this study, we elaborate on those findings by comparing the performances of (i) wet, (ii) Siconi® and (iii) “wet - Siconi®” sequences on re-epitaxy on SiGe surfaces. Those sequences were evaluated on 15 nm thick Si0.6Ge0.4 layers with different Queue-times (15 min and 8 hours) between wet and Siconi® treatments. Without any air break, the Siconi® process was followed by a low temperature H2 bake (at 20 Torr and a temperature less than 700°C) and a re-epitaxy at 600°C of 15 to 17 nm of Si0.6Ge0.4. Secondary Ions Mass Spectrometry (Figure 1) showed that a “chemical oxide - Siconi” sequence yielded a definite reduction of the interfacial oxygen concentration. Even with 8 hours of Q-time, concentrations were very low with these sequences. They were (i) more than one order of magnitude lower than with a regular “HF-HCl” (i.e. a “HF-Last”) wet cleaning and (ii) several times lower than with Siconi® only. Atomic Force Microscopy (AFM) images of the surfaces (Figure 2) of ~ 30 nm thick Si0.6Ge0.4 layers (after epitaxial regrowth) showed the presence of numerous islands after the use of “chemical oxide - Siconi®” surface preparations. Those defects were associated with poor crystalline quality layers. This was surprising. Indeed, such sequences yielded a superior oxide removal efficiency (Fig. 1) and smooth and defects-free SiGe surfaces just after their use (i.e. without any re-growth). Other epitaxial regrowth schemes using solely “HF/HCl” or Siconi® treatments did not result in such defects. The use of “chemical oxide - Siconi®” sequences must have resulted, after oxide removal, in SiGe surfaces richer in germanium than the “bulk” concentration (40%). They were then more sensitive to 2D-3D transitions during the H2 bake than “regular” SiGe 40% surfaces. Ge-rich islands were thus formed during the H2 bake that followed the “chemical oxide-Siconi®” sequence, destabilizing the epitaxial re-growth. In order to prevent surface islanding after "chemical oxide-Siconi®" sequences, we have then evaluated the interest of adding dichlorosilane (DCS) to H2 during the temperature stabilization (just after loading inside the epitaxy chamber), the temperature ramping-up then the H2 bake itself. Our aim was to encapsulate the extreme surface with a few atomic planes of Si in order to prevent 3D transitions. The reason why DCS was used was the following: with this chlorinated precursor, the homo-epitaxial Si growth rate decreased exponentially with the temperature (Ea > 2eV, typically), with a lower “boundary” of 650°C, at which it was only 5 Å/min. When sent on a SiGe surface at T < 650°C, growth with DCS essentially stopped as soon as a switch over to a pure Si surface occurred, resulting in really thin Si caps. The H2 annealing prior to SiGe epitaxy was divided into three steps: 1) low temperature stabilization of the wafer (after loading) ; 2) ramping-up to the bake temperature ; 3) low thermal budget H2 bake (2 min. at T < 700°C). Three epitaxial regrowth schemes, with "HF/HCl-SC1-Siconi®" surface preparations then injections of dichlorosilane during step 1) only, steps 1) and 2) or steps 1), 2) and 3), were evaluated. As shown by AFM (Figure 3), injection of DCS during the various annealing phases drastically reduced the density of 3D defects or suppressed them. The Si spacer thickness between the 15 nm thick Si0.6Ge0.4 layer and the 17 nm of re-epitaxy after the addition of DCS during steps 1) and 2) was 2 nm only (Figure 4). This is acceptable from an integration point of view, especially in SiGe:B sources and drains grown on top of high hole mobility SiGe channels, as such stacks will be germano-salicided afterwards, anyway. Figure 1

International audience; Before metal deposit or epitaxial regrowth steps, efficient surface preparations are mandatory in order to remove both contaminants (C, F) and surface oxides. In this paper, we assess several cleaning sequences and compare their efficiency toward GaAs oxides removal. As III/V materials are very reactive in the air, in-situ surface preparation schemes (conducted for instance in a Siconi chamber) might be useful on GaAs surfaces. This way, the queue-time issues associated with wet surface preparations could be avoided. In this study, GaAs substrates were chemically oxidized to first characterize the oxide removal efficiency of HF, HCl and Siconi processes. Then, a new surface preparation strategy was proposed based on i) a wet chemical treatment followed by ii) a standard Siconi process. In situ Parallel Angle Resolved X-ray Photoelectron Spectroscopy was used to study the chemical composition of the native or chemical oxides and evaluate the impact of the various treatments on the GaAs surface. SIMS analyses were used to measure/quantify the efficiency of surface preparations on Carbon and Arsenic / Gallium oxides removal.

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International audience; The low temperature integration of new materials (such as SiGe channels for the holes) is mandatory in advanced metal oxide semiconductor field effect transistors (i.e. in 14 nm technology node devices and beyond). In this paper, we have investigated the removal of SiGe oxides prior to Selective epitaxial Growth of Si or SiGe:B in Sources/Drains regions. A very efficient removal of contaminants (C, F, O…) is mandatory if the H2 bake that precedes epitaxy is removed because of thermal budget constraints. As germanium is very reactive in the air, in-situ surface preparation schemes (conducted for instance in a Siconi® chamber) might be useful on SiGe surfaces. This way, the queue-time issues associated with “HF-Last” (HF/HCl follow by deionization water rinse) processes in single wafer wet cleaning tools are avoided. Germanium-rich SiGe layers (Si0.6Ge0.4) were used to characterize the native oxide removal efficiency of “HF-Last” and Siconi® processes. Then, a new surface preparation strategy was developed based on i) a wet chemical oxide formation followed by ii) a standard Siconi® process whose efficiency towards SiO2 has conclusively been demonstrated. Parallel Angle Resolved X-ray Photoelectron Spectroscopy was used to study the chemical composition of the native or chemical oxide and evaluate the efficiency of that treatment on carbon, germanium oxide and silicon oxide.

Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique.

The evolution of integrated components in the semiconductors industry is nowadays looking for ultra-high selective etching processes in order to etch high aspect ratio structures in complicated stacks of ultrathin layers. For ultra-high selective processes, typical plasma etching show limitations, while wet etching processes reach limitations due to capillary forces. For these reasons there is a great regain of interest today in chemical downstream etching systems (CDE), which combine the advantages of plasma and wet treatments. The absence of photons and ions allow to minimize damages and to achieve very high selectivity (in isotropic etching). In this work we investigated the parameters enabling to etch selectively the Si3N4 to the SiO2 by CDE. We shown that the correlation between the gas mixture and the wafer temperature is the key to obtain the desired selectivity. In order to optimize the processing window, the mixture composition (NF3/N2/O2/He) and the temperatures were screened by several DOE (Designs Of Experiments). Conditions are found in which the etching selectivity between the two silicon alloys is higher than 100, which allowed us to clean out sacrificial Si3N4 layers in very high aspect ratio (about 100) silicon trenches of nanometric size (60nm) without damaging the 10nm thin SiO2 caping layer (between the Si and the Si3N4). This demonstrates that downstream plasma etching can perform better than wet treatments in this case.

This paper investigates the interest of synchronous pulsed plasmas to etch silicon in HBr/O2 chemistries. Using mass spectrometry, ellipsometry and angle resolved X-ray photoelectron spectroscopy, we demonstrate that the radical concentration in the plasma, the etch rate and formation of passivation layers, can be controlled by the RF pulse parameters (frequency and duty cycle). Accordingly, pattern profiles are improved, selectivity to the mask is increased and the silicon recess is reduced from 4 to 0.8 nm when the HBr/O2 plasma lands on thin silicon oxide.

This work focuses on the impact of oxidizing (O2) and reducing plasma ashing chemistries (NH3, CH4) on the modifications of dielectric materials in a porous or an hybrid state (SiOCH matrix+porogen). The plasma ashing processes have been performed on blanket wafers using O2, NH3, and CH4 based plasmas. The modifications of the remaining film after plasma exposures have been investigated using different analysis techniques such as x-ray photoelectron spectroscopy, infrared spectroscopy, x-ray reflectometry, and porosimetric ellipsometry. For the porous material the authors have shown that NH3 and O2 plasmas induce carbon depletion and moisture uptake while the CH4 plasma only leads to important carbon depletion without moisture uptake and to the formation of a thin carbon layer on the surface. For the hybrid material, no significant material modification is evidenced with the O2 plasma while an important methyl depletion and porogen degradation are observed with reducing chemistries such as CH4 and NH3 plasmas. The impact of the porogen on the film modification and the value of the dielectric constant will be presented and discussed.This work focuses on the impact of oxidizing (O2) and reducing plasma ashing chemistries (NH3, CH4) on the modifications of dielectric materials in a porous or an hybrid state (SiOCH matrix+porogen). The plasma ashing processes have been performed on blanket wafers using O2, NH3, and CH4 based plasmas. The modifications of the remaining film after plasma exposures have been investigated using different analysis techniques such as x-ray photoelectron spectroscopy, infrared spectroscopy, x-ray reflectometry, and porosimetric ellipsometry. For the porous material the authors have shown that NH3 and O2 plasmas induce carbon depletion and moisture uptake while the CH4 plasma only leads to important carbon depletion without moisture uptake and to the formation of a thin carbon layer on the surface. For the hybrid material, no significant material modification is evidenced with the O2 plasma while an important methyl depletion and porogen degradation are observed with reducing chemistries such as CH4 and NH3 pla...

Several issues associated with plasma etching of high aspect ratio structures originate from the ions' bombardment of the sidewalls of the feature. The off normal angle incident ions are primarily due to their temperature at the sheath edge and possibly to charging effects. We have measured the ion velocity distribution function (IVDF) at the wafer surface in an industrial inductively coupled plasma reactor by using multigrid retarding field analyzers (RFA) in front of which we place 400 μm thick capillary plates with holes of 25, 50, and 100 μm diameters. The RFA then probes IVDF at the exit of the holes with Aspect Ratios (AR) of 16, 8, and 4, respectively. The results show that the ion flux dramatically drops with the increase in AR. By comparing the measured IVDF with an analytical model, we concluded that the ion temperature is 0.27 eV in our plasma conditions. The charging effects are also observed and are shown to significantly reduce the ion energy at the bottom of the feature but only with a “minor” effect on the ion flux and the shape of the IVDF.

The aim of the present paper is to review our work on plasma-surface interactions during the etching of silicon gates in low pressure high density HBr/Cl 2 /O 2 based plasmas. In integrated circuit manufacturing, the transfer of patterns onto the polysilicon layer relies on the formation of a passivation layer on sidewalls of the etched features, which protects the silicon gate sidewall from isotropic etching. At the same time, a layer with an almost identical chemical composition is also deposited on the reactor walls and can modify the process parameters by changing the radicals' surface loss probability. In this work we use a new plasma etching-sputtering diagnostic technique, involving a subsequent mild etching of the layer deposited on the chamber walls by a few % SF 6 -containing Ar plasma. Thus we investigate the chemical composition of this layer. This chemical composition is deduced from the time variation of the gas phase concentration of different atoms and radicals, the etch products of the wall deposited layer, monitored during the mild etching of the layer by time-resolved optical emission spectroscopy and mass spectrometry. Optical absorption spectroscopy and mass spectrometry have been employed to characterize the HBr/Cl 2 /O 2 plasma, currently used for the gate etching, and to estimate the absolute flux of neutral and ionic deposition precursors reaching the reactor walls. It comes out that the silicon wafer etch byproducts, SiCl x radicals (x

We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physico-chemical mechanisms involved in plasma etching and deposition.

A new way of operating high-density plasma sources is presented which allows the resist/metal selectivity to be significantly increased during a metal etching process while maintaining the anisotropy of the etching profile. The principle of the technique is to operate a high-density plasma source in a low-density range in which the radio-frequency (rf) source power is lower than the chuck power. When the source is operated under these conditions, the ion density is strongly decreased while the source is still operated at low pressures. Optical emission spectroscopy has been used to compare the dissociation efficiency of the source operated in the low- and high-density modes. The photoresist etch rate was measured using light reflectometry. In some cases, after etching, the resist sample was transferred in vacuo into an x-ray photoelectron spectrometer analysis chamber to measure the chlorine coverage on the resist surface. The ion current density (Ji) was determined using a new type of electrostatic probe. The ion flux was determined from the discharging of a RF-biased capacitance in series with the probe. Finally, a simple model is suggested to explain the impact of the plasma operating conditions (source power and chuck power) on the resist etch rate.

Today porous SiOCH combined with metallic hard masking strategy is an integration of choice for advanced BEOL interconnect technology node. However in this context the main integration issue is the dielectric film sensitivity to fluorocarbon (FC) etch chemistry. In this study, new FC free etching chemistry has been proposed as breakthrough solution. Based on pattern and blanket film analyses, the benefits of this new chemistry is presented and discussed with respect to conventional FC etching. Its compatibility with metallic hard mask integration and wet cleaning is also evaluated.

Plasma etching has been a key driver of miniaturization technologies toward smaller and more powerful devices in the semiconductor industry. Thin layers involved in complex stacks of materials are approaching the atomic level. Furthermore, new categories of devices have complex architectures, leading to new challenges in terms of plasma etching. New plasma processes that are capable to etch ultra-thin layers of materials with control at the atomic level are now required. In this paper, the authors demonstrate that Si etching in Cl2 plasma using plasma pulsing is a promising way to decrease the plasma-induced damage of materials. A controlled etch rate of 0.2 nm min−1 is reported by pulsing the chlorine plasma at very low duty cycles. Using quasi-in-situ angle resolved XPS analyses, they show that the surface of crystalline silicon is less chlorinated, the amorphization of the top crystalline silicon surface is decreased, and the chamber wall are less sputtered in pulsed plasmas compared to continuous wave plasmas. This is attributed to the lower density of radicals, lower ion flux, and lower V-UV flux when the plasma is pulsed.

Since more than 30 years, CW plasmas have been used in the microelectronics industry to pattern complex stacks of materials involved in Integrated Circuit technologies. Even if miniaturization challenges have been successfully addressed thanks to plasma patterning technologies, several fundamental limitations of the plasmas remain and are limiting our ability to shrink further the device dimensions. In this work, we analyze the capabilities of synchronized pulsed ICP technologies and their potential benefits for front end etch process performance. The impact of duty cycle and frequency on the ion energy distribution function and plasma chemistry is analyzed. Our results show that decreasing the duty cycle in ICP plasmas generates less fragmentation of the feed gas stock molecules compared to CW plasmas, leading in final to a decrease of the radical density in the plasma. On a process point of view, we have studied the etching of ultra-thin layers (SiO2, HfO2,SiN spacer) involved in front end processes and investigated what synchronized pulsed plasmas could bring to substrate damage and selectivity issues.

With the emergence of new semiconductor devices and architectures, there is a real need to limit plasma induced damage. This study clearly demonstrates the capability of pulsed plasma technology to minimize plasma induced silicon oxidation that leads to the silicon recess phenomenon during polysilicon gate patterning. Indeed, the authors show that by pulsing optimized continuous wave overetch plasma conditions using HBr/He/O2 plasmas, the silicon recess is reduced from 0.6 to 0.2 nm, while the gate profiles are maintained anisotropic. Synchronous pulsed plasmas open new paths to pattern complex stacks of ultrathin materials without surface damage.

Patterning complex metal gate stack becomes increasingly challenging since the gate dimension for all isolated as well as dense gate structures present on 300 mm wafer needs to be controlled within the nanometer range. In this article, the authors show that SF6/CH2F2/Ar plasma chemistries to etch the polysilicon gate present very interesting critical dimension (CD) control capabilities for advanced gate etch strategies compared to commonly used HBr/O2/Cl2 plasma chemistries, thanks to the different mechanisms involved in the passivation layer formation on the gate sidewalls. Indeed, contrary to HBr/Cl2/O2 plasma chemistries, the passivation layers in SF6/Ar/CH2F2 plasmas are not formed from deposition of etch by-products coming from the gas phase but the passivating species are chemically sputtered from the bottom of the etched structures and coat the silicon sidewalls by line of sight deposition. Such mechanisms result in thin and uniform CFX passivation layers on the gate sidewalls very similar in dense...

The authors have investigated the dry etch mechanisms of complex poly-Si∕TiN∕HfO2 gate stacks and the issues that are correlated with the introduction of a thin metal layer in the gate stack. Based on atomic force microscopy (AFM) and scanning electron microscope measurements, they will first show that a mixture of HBr and Cl2 at low rf bias power is required to successfully pattern the TiN layer without damaging the HfO2 gate oxide. Second, it is demonstrated that the introduction of a metal layer in the gate stack prevents charging effects during the last etching steps of the silicon part of the gate. Transmission electron microscope measurements and x-ray photoelectron spectroscopy analyses of the gate sidewalls show that the thickness of the silicon sidewall passivation layer decreases during the O2 free metal etching step potentially inducing silicon gate profile distortion such as notch. However, the notch can be eliminated by etching the Si∕TiN gate in a single step process instead of stopping at t...

International audience; For the next technological generations of integrated circuits, the traditional challenges faced by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects, …) become more and more difficult, intensified by the use of new materials, the limitations of lithography, and the recent introduction of new device structures and integration schemes. Particularly in the field of the interconnect fabrication, where dual-damascene patterning is performed by etching trenches and vias in porous low-k dielectrics, the main challenges are in controlling the profile of the etched structures, minimizing plasma-induced damage, and controlling the impact of various types of etch stops and hard mask materials. Metallic hard masks can help thanks to their high selectivity toward low-k materials, and by avoiding low-k exposure to potentially degrading ashing plasmas. In this paper, we will present some key issues related to the patterning of narrow porous SiOCH trenches with a metallic (TiN) hard mask. Narrow trenches (down to 40 nm width) can be opened into TiN with a critical dimensions bias (around 10 nm) attributed to carbon and silicon containing deposits on the photoresist and TiN sidewalls during the etching. Porous SiOCH etching using a TiN hard mask instead of the conventional SiO2 hard mask may lead to severe profile distortions, attributed to TiFx compounds which settle on the trenches sidewalls. A chuck temperature of 60 °C and fluorine-rich plasmas are required to minimize those distortions. An etching process leading to almost straight porous SiOCH profiles presenting a slight bow has been developed. However a wiggling phenomenon has been evidenced for the etching of narrow and deep trenches. This phenomenon is attributed to the highly compressive residual stress in the TiN hard mask, which is released when the dielectric is not mechanically strong enough to withstand it.

Wafer-to-wafer reproducibility is a major challenge in gate etching processes. Periodic dry cleaning of the reactor in F-based chemistry between wafers is the most common strategy to ensure process repeatability. However X-ray Photoelectron Spectroscopy analysis of the chamber walls show that this cleaning procedure leaves AlF x species on the reactor walls, eventually resulting in process drifts and formation of particles. We have thus investigated a new cleaning/conditioning strategy of plasma etching reactors, in which the chamber walls are coated by a carbon-rich film between each wafer, allowing stable processing conditions and highly anisotropic etching profile to be achieved in advanced gate stacks. Finally, we present a new method (based on the detection of Cl 2 by laser absorption) to characterize the reactor walls conditions that could prevent process drifts.

This study is dedicated to the etching of a low-k material using the late porogen removal approach. In this approach, the porogen is removed by thermal annealing or UV curing after patterning or copper filling. Starting from a CF4 based plasma, the etch rate decreases with an Ar dilution or by adding a polymerizing gas such as CH2F2. On the other hand, the etch rate increases with O2 or N2 addition in the fluorocarbon gas mixture. X-ray photoelectron spectroscopy analyses show that the etching is controlled by the thickness of the fluorocarbon layer formed at the top surface of the hybrid material during the steady state etch regime. An etch stop phenomenon is even observed with highly polymerizing etch chemistries due to the formation of a thick fluorocarbon layer. Infrared spectroscopy analysis shows that the hybrid film is not damaged by the different etching chemistries investigated in contrast to the porous material.

Summary form only given. The presentation will focus on the dry etch studies required to pattern poly-Si/metal/SiON and poly-Si/metal/high-k gate stacks that might be used in the forthcoming technological nodes. As usual, two key challenges for dry etching metal gate stacks are selectivity and profile control. Smaller and smaller dimensions with more and more complex gate stacks with new materials make those challenges even more difficult. The process development requires the systematic investigation of several etching chemistries and plasma operating conditions for each metal investigated, namely TiN and TaN. In particular, it is necessary to find a plasma chemistry leading to the formation of volatile etch products from the metal layer (to prevent their redeposition on the gate sidewalls, which leads to a tapered profile and CD gain). Another important point is to control precisely the thickness of the passivation layer on the silicon sidewalls during the p-Si etching step. This layer is mandatory to prevent undercutting of the silicon sidewalls (in particular during the metal etching step), but if it becomes too thick sloped sidewalls are generated. To address this issue, XPS analysis of the gate sidewalls passivation layer is performed both after silicon etching and after the full stack patterning. It will be shown that XPS analysis, coupled to SEM and TEM, is a key technique that allows the development of plasma operating conditions that leads to an anisotropic etching profile of the poly-Si/metal gate stack. The other challenge associated with the introduction of the thin metal layer in the gate stack is to obtain a high etching selectivity toward ultra-thin SiON or high-k gate dielectric (HfSiOx and HfO2). As often in plasma etching processes, profile control (anisotropy) and selectivity cannot be achieved under the same plasma conditions. We have investigated the metal/gate dielectric etching selectivities. In this study, AFM measurements coupled to XPS analyses are used to characterize the impact of the gate etch process on the gate dielectric, allowing the development of selective processes free of metallic residues on the dielectric surface. Finally, the dry etch of hafnium based dielectric, when present in the gate stack, is addressed. This very thin (3.5 nm typ.) layer needs to be etched without any induced damage either in the active area (zero Si recess budget) or in the p-Si/metal gate profile previously patterned

This study focuses on the etching characteristics of a TiN hard mask in terms of etch rate and faceting when using a dielectric etch process. The etching experiments have been performed on blanket wafers and patterned structures in an inductively coupled plasma using a conventional CF4∕Ar based plasma. The etch rate and faceting of TiN have been measured as a function of the plasma parameters (bias power and pressure) and also plasma chemistries (Ar dilution and CH2F2 addition). The TiN etch rate is about 30nmmin−1 using the base line process conditions (70SCCM CF4, source power of 500W, bias power of 100W, and pressure of 4mTorr). Lower etch rate is observed at lower pressure and bias power and with higher Ar dilution and CH2F2 addition. The faceting is strongly reduced at lower bias power and higher pressure whereas higher Ar dilution and CH2F2 addition have no clear effect on the facet formation. Surface analysis using x-ray photoelectrons spectroscopy reveal that the top surface of TiN is mainly fluor...

International audience; Plasma etching of HfO2 at an elevated temperature is investigated in chlorine-based plasmas. Thermodynamic studies are performed in order to determine the most appropriate plasma chemistry. The theoretical calculations show that chlorocarbon gas chemistries (such as CCl4 or Cl2–CO) can result in the chemical etching of HfO2 in the 425–625K temperature range by forming volatile effluents such as HfCl4 and CO2. The etching of HfO2 is first studied on blanket wafers in a high density Cl2–CO plasma under low ion energy bombardment conditions (no bias power). Etch rates are presented and discussed with respect to the plasma parameters. The evolution of the etch rate as function of temperature follows an Arrhenius law indicating that the etching comes from chemical reactions. The etch rate of HfO2 is about 110Å/min at a temperature of 525K with a selectivity towards SiO2 of 15. x-ray photoelectron spectroscopy analyses (XPS) reveal that neither carbon nor chlorine is detected on the HfO2 surface, whereas a chlorine-rich carbon layer is formed on top of the SiO2 surface leading to the selectivity between HfO2 and SiO2. A drift of the HfO2 etch process is observed according to the chamber walls conditioning due to chlorine-rich carbon coatings formed on the chamber walls in a Cl2–CO plasma. To get a very reproducible HfO2 etch process, the best conditioning strategy consists in cleaning the chamber walls with an O2 plasma between each wafer. The etching of HfO2 is also performed on patterned wafers using a conventional polysilicon gate. The first result show a slight HfO2 foot at the bottom of the gate and the presence of hafnium oxide-based residues in the active areas.

High quality Ta2O5 thin films have been obtained from TaF5 and O2 using a microwave excited electron cyclotron resonance plasma at low pressure (∼2 mTorr). Physical and electrical measurements reveal that the as‐deposited amorphous films have excellent properties: refractive indices ∼2.16, dielectric constants ∼25, and leakage currents

During plasma etching processes, organic or mineral layers are deposited on the chamber walls. In general, these layers cause large and uncontrolled shifts in the etch process, which is becoming a major issue in some of the plasma processes used in integrated circuit fabrication. The chemical nature of these layers and their deposition mechanisms remain poorly understood due to the lack of in situ surface diagnostics available to monitor the reactor walls. In this article, we present a simple technique using x-ray photoelectron spectroscopy (XPS) analyses to monitor the chemical composition of the layer deposited on a sample floating on top of a 200-mm-diam wafer where the layers deposited are identical to those deposited on the chamber walls. The principle of the technique is to stick a small Al2O3 sample onto the 200-mm-diam silicon wafer, with an air gap between the sample and the wafer. Providing that the air gap is thick enough, the Al2O3 surface will be electrically floating even when the silicon wa...

Critical dimension (CD) control during silicon gate etching has been investigated with state-of-the-art chemistries. In particular, we have compared the etched profile of both isolated and dense gates obtained after the main etch step of a gate etch process using HBr/Cl2/O2 and HBr/Cl2/O2/CF4 gas mixtures, and study the influence of the CF4/O2 ratio in this mixture. We demonstrate that the gate etch profile is mainly driven by the passivation layer deposited on the gate and mask sidewalls during the etching. Due to aspect ratio dependant etching effect the passivation layer formation is thinner in dense than in isolated structures resulting in significant profile microloading. However, CF4 addition to HBr/Cl2/O2 strongly minimizes the difference in passivation layer thickness between dense and isolated lines thus potentially improving the critical dimension control. These results will be discussed in terms of chemical composition of the passivation layer and deposition mechanisms, based on previous studie...

In less than 10 years, we will be approaching the limits of CMOS technology with transistor gate length between 20 and 30 nm. The definition of the transistor gate region will remain one of the most critical steps of the device fabrication process since the final gate dimension cannot be derived from the dimension targeted by more than few nanometers. Etching of silicon gates is achieved in high density plasmas, allowing vertical profiles to be obtained, transferring the critical dimensions (CD) obtained after lithography. The ultimate resolution of this approach is limited by the lithographic performance of the exposure tool and by the etching process. In the present paper, we present a new type of process allowing the design of gates having a bottom dimension smaller than the top dimension (the so-called ‘notched gate’). We discuss the design of the notched gate process with respect to a standard gate etch process and give some details on the sidewall passivation layer engineering. Finally, some results of CD control across a 200-mm diameter wafer are shown and the potential implementation of the process in pilot lines is discussed.

Broadband ultraviolet absorption spectroscopy of the weak Cl2 continuum between 250 and 400 nm was used to measure the molecular Cl2 density in pure chlorine inductively coupled plasmas at pressures of 15–100 mTorr and radio-frequency (rf) power up to 800 W. The depletion of the Cl2 density was greatest at high-rf power and low pressure, and reached 80% at 15 mTorr 800 W. A simple global model was developed to explain the variation of the Cl2 dissociation rate as a function of source power and total gas pressure, and was in excellent agreement with the observations.

In less than ten years, we will be approaching the limits of the complementary metal-oxide-semiconductor technology with transistor gate length of between 10 and 30 nm. In the present article, we present a type of process allowing the design of gates having a bottom dimension smaller than the top dimension (the so-called “notched gate”). We discuss the design of the notched gate process with respect to a typical gate etch process and give some details on the sidewall passivation layer engineering. Finally, some results of critical dimension control across a 200-mm-diam wafer are shown and the potential implementation of the process in manufacturing is discussed.

We have studied the etching of low dielectric constant polymers in halogen- and sulfur-free chemistries under various plasma operating conditions. The polymer graphitization phenomenon, which corresponds to the transformation of the aromatic hydrocarbon network into an amorphous carbon backbone, has been fully investigated under several plasma conditions by in situ mass spectrometry and quasi-in situ x-ray photoelectron spectroscopy (XPS). Profile control in high aspect ratio contact holes is obtained thanks to the formation of a passivation layer on the polymer sidewalls preventing the spontaneous chemical attacks by the oxygen reactive species of the plasma. XPS studies show that the passivation layer only forms under conditions where the plasma induces a polymer graphitization. Strong correlations are observed between plasma conditions leading to the polymer graphitization, the presence of heavy carbon byproducts detected in the plasma gas phase, and the passivation layer formation.

We have studied the etching of very high aspect ratio contact holes in hydrocarbon materials SiLK™, potential dielectric candidates for the next generation of interconnections. During the etch process, slight deformation of the etch profiles such as bowing are observed. Experiments described in this article suggest that bowing originates from the deflection of ions on the sidewalls of the polymer, generating some etching. The mechanisms leading to the ion deflection on the sidewalls are presented and discussed. This study also shows how the process can be tuned to minimize the bow formation.

We have used x-ray photoelectron spectroscopy (XPS) to investigate the composition of sidewall passivation films formed during the plasma patterning of 0.1 μm silicon gates in a high density plasma source, as a function of plasma operating conditions for HBr, Cl2, and O2 based chemistry. XPS analyses clearly show that sidewall passivation films SiXxOy (X=Br, Cl, x+2y⩽4) are formed during the main step of the gate etch process and become oxidized at the early stage of the overetch step leading to an oxidelike layer after halogen desorption. Sidewall passivation films are thicker under HBr based chemistry than under chlorine containing chemistries. In addition, the film thickness seems to be highly sensitive to oxygen dilution in HBr based plasma. These results are discussed in view of the critical dimension deviation budget bearable in sub-0.1 μm gate fabrication.

Direct nitridation of the silicon substrate using gaseous NO at 550–700°C, 10 mbar is studied using physical (SIMS, TEM, XPS) and electrical characterisations. The nitrogen profile can be tailored for the fabrication of thin nitrided oxides as in the case of implanted nitrogen. Degradation of the I(V) characteristics has been evidenced when the nitrogen amount increases.

Plasma etching is the most standard patterning technology used in micro- and nano-technologies. Chlorine-based plasmas are often used for silicon etching. However, the behavior of thin silicon oxide exposed to such a plasma is still not fully understood. In this paper, we investigate how a thin silicon oxide layer on silicon behaves when it is exposed to a Cl2 plasma. The authors show that chlorine atoms diffuse and/or Cl+ ions are implanted through the thin (

We have evidenced an unexpected behavior of thin gate oxide layers (thickness in the range 2–4 nm) exposed to plasma processes developed for the patterning of 0.1 μm silicon gates. During the low-energy overetch step of the process, an oxidation of the bulk underlying silicon takes place, leading to the growth of the gate oxide layer. Experimental results obtained from in situ kinetic and spectroscopic ellipsometry measurements and supported by x-ray photoelectron spectroscopy analyses are presented to highlight this phenomenon.

BCl3 based plasmas exhibit promising plasma chemistries to etch high-k materials and, in particular, HfO2, with a high selectivity over SiO2 and Si substrates. The authors report on the mechanisms involved in the etching of HfO2, SiO2, and poly-Si substrates in BCl3 plasmas. X-ray photoelectron spectroscopy analyses help in understanding the mechanism driving the high etch selectivity between HfO2 and silicon-containing substrates. The ion energy plays an important role in the etching mechanisms since it controls a transition between a BCl-like deposition on the substrate and its etching by ionic bombardment. The ion energy threshold above which etching occurs is different from one substrate to another, being lower for HfO2 than for Si substrates. Indeed, BClx deposition forms more easily on poly-Si or SiO2 rather than on HfO2 surfaces, because boron reacts with Si atoms to form Si–B bonds initiating the growth of BClx polymer on Si-containing surfaces, while on HfO2 surfaces, boron is directly involved i...

This article demonstrates that a 10 nm isolated silicon pattern on a very thin gate can be achieved if the plasma parameters and chemistry that impact the critical dimension (CD) control are well understood. The parameters investigated are the passivation layers that form on the silicon gate sidewalls which directly impact the CD control, the nature of the mask used during the gate process (resist mask or SiO2 hard mask), the charging effects developed when the plasma lands on a thin gate oxide.

We have used x-ray photoelectron spectroscopy (XPS) to investigate the resist patterns’ transformation after exposure to reactive plasmas and we have correlated the resist modifications with the process performance obtained by scanning electron microscope (SEM) observations. The experimental procedure based on the chemical-topography analysis of resist patterns using XPS has been used to determine the chemical composition and thickness of the reactive layers that are formed both on the tops and sidewalls of the resist features during the plasma process. This method was then applied to a variety of processes used in integrated-circuit fabrication. For all the processes analyzed [resist-trimming process in high-density plasma, bottom-antireflective-coating (BARC) opening process in a medium-density plasma and thin SiO2 hard-mask-opening processes in both plasma sources], we have observed very good correlations between XPS results and the evolution of the resist-patterns’ dimensions during plasma exposure. I...

We have used x-ray photoelectron spectroscopy (XPS) to analyze resist patterned silicon surfaces etched in a commercial 200 mm high density plasma etcher. After anisotropic etching using gate etching chemistries based on HBr/Cl2/O2 gas mixtures with or without CF4 addition, wafers are transferred under vacuum to perform chemical topography analysis using XPS in order to measure the element concentration on the silicon surfaces at the bottom of the trenches as well as the silicon sidewalls. Composition of the layers formed on the silicon sidewalls as a function of the plasma operating conditions is reported and discussed. The sidewall layer formation is mainly attributed to the oxidation of silicon etching by-products and the deposition of fluorocarbon species. Depending on the O2 and CF4 amount during a silicon gate main etch step, composition of the layer can be either SiOx-like or fluorocarbon rich. In all cases, the sidewall layer is transformed into a SiOx material during the subsequent fluorine free ...

This study is dedicated to an analysis of the etch mechanisms of SiOCH, SiO2 and SiCH in fluorocarbon plasmas. The etching of these materials is performed on blanket wafers in a magnetically enhanced reactive ion etcher reactor using fluorocarbon based chemistry (CF4/N2/Ar). After partial etching, the Fourier transform infrared spectroscopy and mercury probe measurement indicate that the remaining substrate of SiOCH is not altered by the reactive plasma. A decrease in the etch rate of SiOCH, SiO2 and SiCH is observed either with increasing Ar dilution or polymerizing gas addition as CH2F2 and C4F6. X-ray photoelectron spectroscopy analysis of the surface after partial etching shows that the thickness of the fluorocarbon layer formed at the film surface and its composition play a key role in controlling etch rate and selectivity of SiOCH, SiO2 and SiCH. The etch rate of these materials is getting lower when the fluorocarbon layer thickness increases and also when its fluorine concentration decreases. The f...

Anisotropic etching of silicon gates is a key step in today’s integrated circuit fabrication. For sub-100 nm gate dimensions, one of the main issues is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physicochemical mechanisms involved in anisotropic plasma etching. Since silicon etching in high-density plasmas is strongly ion assisted, the identities of the ions bombarding the wafer is a key parameter that governs the etch rates and the etched profiles. In the present article, mass spectrometry has been used to investigate the chemical composition of the ion flux bombarding the reactor walls of an industrial inductively coupled plasma used for 200-mm-diam silicon wafer processing. The plasma chemistries investigated are HBr/Cl2/O2 and HBr/Cl2/O2/CF4 mixtures optimized for sub-100 nm gate processes. Quantitative ion mass spectra show that under those conditions the ion flux contains up to 50% of SiClXBrY+ (X,Y=0–2) ions, although Cl+, Cl2+, and Br+ i...

Gate structures with dimensions smaller than 0.1 μm on gate oxides thinner than 2 nm have been patterned in a high density plasma helicon source. The chemistry which seems best adapted uses an HBr/O2 mixture ensuring high selectivity to the gate oxide and an etch anisotropy allowing the critical dimension control in the 0.1 μm regime to be acceptable. Kinetic ellipsometry has been used to measure silicon and SiO2 etch rates and carefully control the process in real time. X-ray photoelectron spectroscopy (XPS) studies have been performed to determine the chemical topography of SiO2 masked gate stacks with different aspect ratios. In particular, the chemical composition and thickness of the sidewall passivation layer have been determined. We have also observed an unsuspected behavior of thin gate oxides during the overetch step of the process. By combining XPS and spectroscopic ellipsometry, we have attributed this behavior to reactive species penetration through the thin gate oxide. This phenomenon could p...

We have used x‐ray photoelectron spectroscopy (XPS) to study the chemical constituents present on the surfaces after etching of poly‐Si features masked with photoresist. Poly‐Si etch rates were determined using in situ HeNe laser ellipsometry. The wafers were etched in a low pressure, high density plasma, helicon source using a chlorine/helium gas mixture. The XPS analysis chamber is connected to the reactor chamber via an ultrahigh vacuum chamber allowing quasi in situ analysis of the etched samples. Electrostatic charging of insulating surfaces and geometric shadowing of photoelectrons by adjacent photoresist lines have been used to differentiate photoemission signals from the tops, sidewalls, and bottoms of the features. Blanket and photoresist masked poly‐Si samples were etched without biasing the substrate. The poly‐Si etch rate decreased as a function of etching time and finally stopped due to the deposition of an oxide film. When biasing the sample, etching occurred and anisotropic etching profiles...

High density plasma etching processes using chlorine gas have been developed for 0.25 μm polysilicon etching. Polysilicon films on SiO2‐covered 200 mm silicon wafers are masked with photoresist patterns, and then etched downstream using a high density helicon source made by Lucas Labs of Sunnyvale, CA. To enhance the anisotropic etching, ion bombardment is provided by radio frequency (rf) biasing of the sample. Polysilicon trenching can be suppressed by performing a two‐step etching process: the first uses a high energy ion bombardment resulting in high etch rate (250 nm/min) and anisotropy and the second a lower ion energy. The second etching step shows a high selectivity (≳80) of Si over SiO2 and therefore ensures the complete removal of the polysilicon during the overetch time. Perfect anisotropic profiles can be obtained without any trenching or other undesirable anomalies. The optimum etch rate nonuniformity is 6.5% (3σ) when operating the source at maximum rf source power (2500 W), 2 mTorr reactor p...

Plasma oxidation of the c-Si substrate through a very thin gate oxide layer can be observed during HBr/O2/Ar based plasma overetch steps of gate etch processes. This phenomenon generates the so-called silicon recess in the channel and source/drain regions of the transistors. In this work, the authors compare the silicon recess generated by continuous wave HBr/O2/Ar plasmas and synchronous pulsed HBr/O2/Ar plasmas. Thin SiO2 layers are exposed to continuous and pulsed HBr/O2/Ar plasmas, reproducing the overetch process conditions of a typical gate etch process. Using in situ ellipsometry and angle resolved X-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess can be reduced from 4 to 0.8 nm by pulsing the plasma in synchronous mode.

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Selective etching process by remote plasma meet an increasing interest for integration schemes used to develop the latest technology nodes in the microelectronic industry. Those processes offer high and flexible selectivities, and in the meantime etching rates compatible with industrial applications. Nevertheless chemical reactions involved are not well understood and real potentials of this method probably underestimated. In this context, a new CDE chamber is being currently installed at the LTM labs (CNRS)., Les procédés de gravure sélectives par plasma déporté rencontrent un intérêt croissant pour les schémas d’intégration des nœuds technologiques en développement pour la micro-électronique. Ces procédés offrent des sélectivités importantes et modulables pour des vitesses de gravure compatibles avec des retraits de couches d’épaisseur très variables.Néanmoins les processus mis en jeu sont encore mal connus et les potentialités restent à estimer. Dans ce contexte, une chambre de gravure à plasma déporté est en cours d’installation sur une plateforme de gravure au LTM.

The miniaturization of microelectronics devices requires the development of ever more accurate etching processes. The subject of this thesis is part of this problematic: a controlled sequential etching process at the nanoscale has been developed to overcome the inherent defects of direct plasma etching. This etching process intended in our case for the etching for SiN spacers, is divided in two steps. The first step is a light atom implantation. The implantation of light chemical species such as Hydrogen or Helium has the advantage of modifying the structure of the material without inducing a damaging sputtering for the device to be etched. In the second step, the layer modified by the implantation is etched selectively regarding the pristine material via a remote plasma.Hydrogen implantation was mainly studied during this work: different characterizations to quantify the implanted hydrogen as well as the modified thickness were carried out. X-ray reflectometry measurements were used to determine the modified thickness as a function of the self-polarization power and the duration of implantation. Hydrogen implant profiles on SiN were also carried out through electrical characterizations. The charge density profiles observed were compared to Si-H and N-H bond profiles obtained from infrared spectroscopic measurements in multiple reflections. These measurements were also compared to secondary ionization mass spectrometry profiles. These profiles make it possible to quantify implanted hydrogen as a function of depth, and have also provided information regarding the influence of UV radiation and the chemical configuration of the implanted material. A significant presence of oxide on the surface of the implanted material has also been observed through X-ray photoelectron spectroscopic measurements.The removal step was mainly studied via kinetic ellipsometric in situ measurements and X-ray photoelectron spectroscopic measurements for different temperature conditions and for different chemical mixtures. The ellipsometric measurements made it possible to observe the formation of salts during etching, whereas the X-ray photoelectron spectroscopic analysis showed that the surface of the material was deoxidized by the remote plasma, while a large quantity of fluorine was measured at the same time on the material surface. The studies carried out on the implantation and removal steps made it possible to succesfully etch patterned samples under the appropriate conditions., La miniaturisation des dispositifs de la microélectronique nécessite la mise au point de procédé de gravure toujours plus précis. Le sujet de cette thèse s’inscrit dans cette problématique, en effet un procédé de gravure séquentielle contrôlée à l’échelle nanométrique a été proposé pour pallier aux défauts inhérents à la gravure plasma directe. Ce procédé de gravure destiné dans notre cas à la gravure d’espaceurs en SiN, se décompose en deux étapes. La première étape est une implantation d’atome léger. L’implantation d’espèces chimiques légères telles que de l’Hydrogène ou de l’Hélium présente l’avantage de modifier la structure du matériau sans induire une pulvérisation dommageable pour le dispositif à graver. La couche modifiée par l’implantation est ensuite gravée de manière sélective vis-à-vis du matériau pristine via un plasma « downstream » ou plasma déporté.L’implantation d’hydrogène ayant principalement été étudiée au cours de ces travaux, différentes caractérisations visant à quantifier l’hydrogène implanté ainsi que l’épaisseur modifiée ont été réalisées. En effet, des mesures de réflectométrie des rayons X ont permis de déterminer l’épaisseur modifiée en fonction de la puissance d’autopolarisation ainsi que de la durée d’implantation. Des profils d’implant hydrogène sur du SiN ont également été effectués au travers de caractérisations électriques. Les profils de densité de charge obtenus ont été comparés à des profils de liaisons Si-H et N-H obtenus à partir de mesures spectroscopiques infra-rouge en réflexion multiple, et ces mesures ont également été comparées à des profils de spectrométrie de masse à ionisation secondaire. Ces profils permettent de quantifier l’hydrogène implanté en fonction de la profondeur, et ont également fournis des informations vis-à-vis de l’influence du rayonnement UV et de la configuration chimique du matériau implanté. Une présence significative d’oxyde à la surface du matériau implanté a également été observée par le biais de mesures spectroscopique de photoélectrons X.L’étape de retrait a principalement été étudiée via des mesures ellipsométriques cinétiques in situ, et des mesures spectroscopique de photoélectrons X pour différentes conditions de température, et pour différents mélanges chimiques. Les mesures ellipsométriques ont permis d’observer la formation de sels durant la gravure, alors que les analyses spectroscopiques de photoélectrons X ont montré que la surface du matériau été désoxydée par le plasma de retrait, parallèlement une quantité importante de fluor a été mesurée à la surface du matériau.Les études réalisées sur les étapes d’implantation et de retrait ont permis de graver de manière satisfaisante des échantillons patternés dans les conditions adéquates.

Since its beginning, the microelectronic industry is aiming to increase the circuits performance and density, following Moore’s law. Hence, since the commercialization of the first circuit in 1971, the industry focuses on the transistor dimensions reduction, which improve the device performances. But, starting from the 28nm technological node, the electrostatic has become very difficult to control, and new device structure, such as the FDSOI, is proposed by STMicroelectronics to resolve this issue. The antenna effects, which occur during plasma processes, induce gate oxide damages, which can lead to the loss of those new technology benefits. In this context, the analysis of this phenomenon on the electrical behavior of FDSOI devices is key. This is the main objective of this work. First, an experimental protocol is defined, based on plasma processes characterization technique (antenna structures), and gate oxide damage characterization. Then, a charging flow mode specific to this new technology is proposed. The mechanisms linked to the antenna damages are also investigated. The first mechanism is linked to the plasma local nonuniformity between the device nodes, which induces a stress mode similar to hot carrier injection. The second mechanism is related to the antenna topography, which generates electron shading effect, thus promoting an electrical imbalance between the device nodes. Finally, a model based on the simulator circuit ELDO ®, which allows reproducing the behavior of this phenomenon on the FDSOI technology is proposed. This model takes into account the antenna structure characteristics and the plasma parameters. Based on the model simulations, various solutions to reduce the antenna voltages are proposed. Prevention rules during the circuit design were also proposed and implemented., Depuis ses débuts, l’industrie de la microélectronique s’est fixé comme objectif d’augmenter les performances et la densité des circuits, en suivant la loi de Moore. Ainsi, depuis la commercialisation du premier circuit en 1971, les industriels se sont atteler à miniaturiser les transistors, ce qui améliore automatiquement leurs performances. Cela dit, à partir du nœud 28nm, l’électrostatique est devenue très difficile à contrôler, et de nouvelles architectures de transistor, tel que le FDSOI est proposée par STMicroelectronics pour remédier à cette problématique. Les dégradations par effets d’antenne, qui apparaissent lors des procédés plasma, provoque la dégradation de l’oxyde de grille des composants, et peuvent ainsi induire la perte des avantages offerts par cette nouvelle technologie. Dans ce contexte, l’évaluation de l’impact de ce phénomène sur le comportement électrique des transistors en technologie FDSOI est clé. Cela représente l’objectif principal de cette thèse. Tout d’abord, un protocole expérimental a été défini, basé sur des techniques de caractérisation des procédés plasma (structures d’antenne), et sur la caractérisation de la dégradation de l’oxyde de grille. Ensuite, un nouveau mode d’écoulement des charges durant les étapes plasma, spécifique à cette nouvelle technologie est proposé. Le comportement des principaux mécanismes de dégradation par effet d’antenne est aussi investigué. Le premier, est lié à la nonuniformité locale du plasma entre les nœuds du transistor, qui induit des dégradations de type porteurs chauds. Le second, est lié à la topographie des antennes, qui cause des effets d’ombrage électronique, et donc des déséquilibre en courant entre les nœuds du transistor. Enfin, un modèle basé sur un simulateur de circuit ELDO ®, et qui permet de reproduire le comportement de ce phénomène dans la technologie FDSOI est proposé. Ce dernier tient compte des caractéristiques des structures d’antenne ainsi que des paramètres plasma. Diverses solutions sont par la suite proposées pour réduire les tensions d’antenne, basées notamment sur des simulations modèles pour optimiser les paramètres des procédés plasma. Des solutions de prévention dès la conception des circuits sont aussi proposées.