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2. Reflectometry in the ITER Divertor

3. Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below

5. FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

12. Electrical characterization of Si nanocrystal devices suitable for RT-SET operation

13. Ultrathin n+/p junction in preamorphized silicon by phosphorous and carbon coimplantation engineering: influence of C location

14. A comprehensive platform for thermal studies in TSV-based 3D integrated circuits

15. First CMOS Integration of Ultra Thin Body and BOX (UTB2) Structures on Bulk Direct Silicon Bonded (DSB)

16. TORE SUPRA Team Mmembers 1988-2008

17. Planar Bulk+ Technology using TiN/Hf-based gate stack for Low Power Applications

18. Pushing Bulk Transistor with Conventional SiON Gate Oxide for Low Power Applications

19. Shallow junction engineering by phosphorus and carbon co-implantation: optimization of carbon dose and energy

20. Ultra shallow junctions optimization with non doping species co-implantation

23. Thermal correlation between measurements and FEM simulations in 3D ICs

24. Science and technology research and development in support to ITER and the Broader Approach at CEA

25. 3D Integration challenges today from technological toolbox to industrial prototypes

27. WSS and ZoneBOND temporary bonding techniques comparison for 80μm and 55μm functional interposer creation

28. Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

29. Challenges and solutions for ultra-thin (50 μm) silicon using innovative ZoneBOND™ process

31. Contribution of Tore Supra in preparation of ITER

32. Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below

33. First CMOS integration of ultra thin body and BOX (UTB2) structures on bulk direct silicon bonded (DSB) wafer with multi-surface orientations

35. Investigation of steady-state tokamak issues by long pulse experiments on Tore Supra

36. Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

37. FDSOI devices with thin BOX and ground plane integration for 32nm node and below

40. Pushing Bulk Transistor with Conventional SiON Gate Oxide for Low Power Applications

41. Effect of Poly/SiON Gate Stack Combined with Thin BOX and Ground Plane for Low Vth and Analog Applications of FDSOI Devices

42. Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications

44. Folded fully depleted Bulk+ technology as a highly W-scaled planar solution

45. FDSOI devices with thin BOX and ground plane integration for 32nm node and below

46. Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm2 6T-SRAM bitcell

48. Highly Manufacturable and Cost-effective Single TaxC / HfxZr(1-x)O2 Gate CMOS Bulk Platform for LP Applications at the 45nm Node and Beyond

49. CMP-less Co-Integration of Tunable Ni-TOSI CMOS for Low Power Digital and Analog Applications

50. A Cost-Effective Low Power Platform for the 45-nm Technology Node

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