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GaN-on-Si HEMT technology suffers from RF losses and non-linearities originating from the conductive Si substrate. The understanding and modeling of substrate performance are the keys to enabling next-generation front-end modules. In this letter, we show that when subjected to a chuck bias step, the effective substrate resistivity of a typical C -doped HEMT stack shows a dynamic behavior. Using a dedicated setup, stress/relaxation sequences at different temperatures are performed to understand this phenomenon. With the help of TCAD simulations, it is shown that redistribution of charges trapped in deep defects located in the III-N buffer can qualitatively explain the observed trends. Trap activation energies of 0.43 and 0.33 eV are extracted from measured data.

Hybrid electromagnetic (EM) and thermal imaging using spintronic technologies is proposed for sensing circuits and systems in near-field and far-field from DC (Switching-Power) to mmWave frequencies. High resolution spintronic sensors capable of detecting magnetic fields ranging from few tens of mT (milli-Tesla) down to tens of pT (pico-Tesla) are demonstrated spanning about 10 orders of magnitude in dynamic range. A configurable Agile Front-End-Module LNA (AFEM) is combined with spintronics probe-array sensors providing adjustable 80 dB of dynamic range for subsequent processing of MIMO correlations in time and frequency domains. The proposed hybrid EM-Thermal sensing solution is applied to mmWave beamforming modules demonstrating the possibility of extracting power-density and energy-density metrics as a function of beamforming angles. An infrared (IR)- Visual dual-camera is introduced together with augmented reality (AR) based on 3D non-uniform spatial-sampling. Porting of chemically functionalized spintronic sensing materials into advanced FD-SOI platforms is proposed using advanced MRAM/SRAM process technologies.

A DC-120 GHz SPDT switch is proposed using GlobalFoundries’ 22FDX® SLVT devices with improved substrate isolation rings. For mm-wave switch applications, 22FDX® offers BFMOAT devices that include substrate isolation zones beneath them to reduce high-frequency shunt loss, though, compared to SLVT devices, this sacrifices the back-gate functionality, resulting in higher R onCoff . This paper proposes and analyses substrate isolation zones implemented in ring- shapes around SLVT-FETs to reduce parasitic shunt admittance while preserving the back-gate. The resulting effective device boasts a low RonCoff metric (thanks to an SLVT-FET core with back-gate) and simultaneously achieves high substrate impedance to the reference ground node (similar performance as BFMOAT-FETs). From such devices, a full SPDT switch was fabricated and characterized up to 130 GHz. Having less than 2.4 dB insertion loss and better than 22 dB isolation from DC to 120 GHz, it outperforms analogous SPDT modules implemented using conventional SLVT or BFMOAT FETs.

In this paper, we propose hybrid GaN-FDSOI Front-End-Modules (FEMs) combined with lens-based mmWave antenna modules for energy-efficient multi- beamforming systems. X-topology Lattice-based balanced (LB) and unbalanced (LU) differential switches are designed and fabricated using FDSOI platforms for building scalable multi- beamforming FEMs. Unified mmWave and Baseband correlation technologies based on energy density and EVM (Error Vector Magnitude) metrics are introduced for low complexity (leveraging sparsity of MIMO channels) cost-effective multi-beamforming systems. Combination of convolutional accelerators with analog signal processing for linking beam- selection algorithms to stochastic-wave-shaping (SWS) will create new paradigms for eliminating the concept of “elements” in arrays and replacing it by the vision of “radiating current flows” over a textured surface (metasurface or metavolume). The radiating metasurfaces or metavolumes which can be conformal to the patterned optical lenses are fed by a limited number of emitting/receiving points. The use of time-modulated correlation functions will foster new system architectures with critical functionalities including direction of arrival (DOA) estimation and secure communications.

The measurement of series extrinsic resistances of MOSFETs is not straightforward and the gate resistance (Rg) in particular is very sensitive to noise measurement and measurement inaccuracies. They are critical elements that need an accurate estimation for proper FET modeling and RF figures of merit assessment, as they limit the extrinsic cutoff and maximum oscillation frequencies (ft, fmax) in deeply scaled CMOS technologies. This work compares the extrinsic resistances extraction with different off-wafer and on-wafer calibration and de-embedding methods to provide an insight on the appropriate procedure for accurate correction. Then, measurements obtained with three different probe technologies are compared. A resonance-like signature specific to each probe technology is observed, caused by unwanted coupling between the probe and the on-chip neighbor environment of the test structures. This coupling is not well corrected by the calibration and de-embedding procedure and is reflected back on the corrected measurements, mainly on the fmax and Rg curves. Overall, the best probe technology for DC-110 GHz measurements among the probes tested in this work is identified to be Picoprobe, featuring a gate resistance extraction with less than ±3% variation from 10 to 60 GHz.

This paper presents a 2-stage low-noise amplifier (LNA) designed in 22 nm fully-depleted silicon-on-insulator (FD- SOI) technology, covering the N259 and N260 millimeter-wave 5G bands. The prototype features 19.9 dB peak gain, 2.5-2.6 dB noise figure (NF) and 6.6 GHz bandwidth (intersection of 3 dB gain flatness and -10 dB input/output matching), -5.4 dBm third- order input intercept point (IIP3) for a 20.8 mW power dissipa- tion. Modulating the back-gate bias of each stage independently switches the LNA operation mode from a combination of low- noise (0.8 dB variation in NF), high-linearity (~3 dB variation in IIP3) and/or low-power (down to 7.4 mW). Finally, a careful noise contribution analysis of the input matching identifies a 0.58 dB main contribution from the input spiral inductor. EM simulations show that a 0.06 dB improvement in NF can be achieved by using a high-resistivity substrate, if the input inductor design is optimized by stacking several metal layers. Keywords—Low-noise amplifier, FD-SOI CMOS, millimeter- wave, Back-gate bias, 5G, spiral inductor.

The quality factor (Q) of two inductors for 5–60 GHz applications fabricated in an industrial back-end of line (22FDX® from GlobalFoundries) with thick Cu metal layers on top of several Si substrates of different bulk resistivities is analyzed in this paper. The low frequency RF inductor shows an improvement of up to 44% in Q with a high-resistivity substrate. However, no significant improvement is observed for the high-frequency MMW fabricated inductor. This is identified to be due to lower electric field concentration in the substrate due to the small geometry of this MMW inductor that is realized in the top metal Cu layer. Nevertheless, simulations show that a 30% improvement can be achieved with a low loss substrate when designing a MMW inductor as a stacked coil of all BEOL thick metal layers.

This paper presents a novel 28 GHz down- conversion mixer topology using the back-gate terminal in 22 nm FD-SOI as an RF excitation port for the 21 GHz local oscillator (LO) signal. A double balanced architecture with an active load and transimpedance amplifier were implemented in the 22FDX® technology from GlobalFoundries. The mixing functionality is provided at the level of a single FET, that is simultaneously excited at the front- and back-gates by the RF and LO signals, respectively. Under 0.9 V power supply (26 mW DC consumption) the proposed down-conversion mixer exhibits a maximum conversion gain of 3.5 dB by applying 10 dBm of LO power. The 1 dB compression point occurs at -6 dBm of RF input power and the third order intercept (IIP3) point is 15 dBm at nominal LO power. Benchmarking these values against mixer performances from the literature reveals this design to be close to the current state-of-the- art in CMOS and SOI technology, demonstrating the viability of this novel topology employing back-gate excitation at mm-wave frequencies

FD-SOI is a promising technology for integrating mm-wave front-end circuitry. In this paper, fully-differential SPST and SP4T switches are designed with wideband operation (DC up to 50 GHz) using GlobalFoundries’ 22FDX® platform. Based on a differential mode-blocking topology, the switches can achieve isolations better than 50 dB. At 28 GHz, the balanced topology achieves an insertion loss of 1.92 dB, a 1-dB compression of 23.5 dBm and an IIP3 of 47.6 dBm.

RF reliability at 28GHz in PAFETs under constant and varying output load (Z0) was evaluated. Time domain analyses show that in addition to non-conducting TDDB (ncTDDB), both conducting (cHCI) and non-conducting Hot Carrier Injection (ncHCI) degradation play key roles as primary mechanisms. RF power as stress variable under linear, P1dB and compression shows higher degradation in compression attributed to higher peak voltage swings. Degradation under varying load is correlated to ruggedness power and VSWR ratio. Excellent DC and RF Model-Hardware correlation was achieved. 5G NR simulations show that PAFETs meet circuit PA lifetime targets making it an ideal technology for mmWave 5G applications.

At high frequency, the accurate modelling of parasitic elements is crucial to IC design. Substrate behavior is a significant contributor to such parasitics, and its modelling is a challenge, not only under small-signal conditions due to strongly non-uniform resistivity profiles in semiconductor materials, but especially under large-amplitude excitations. In this work, substrate impact on a variety of pertinent integrated devices is studied, under both small- and large-signal conditions. To do so, the effective resistivity and linearity parameters are defined as RF substrate figures of merit, and their extraction procedures are described. These figures of merit serve as reliable indicators of substrate loss, coupling, and induced signal distortion. It is required that such considerations be kept under careful control in front-end circuitry for advanced telecommunication applications that have stringent spectral cross-contamination specifications between adjacent communication bands. In this thesis, both small- and large-signal modelling approaches are developed to account for such substrate effects. The developed models are heavily based in material semiconductor physics, and, in this work, the physical charge-balance interplay is rigorously studied, shedding light on the inner workings of a wide range of silicon-based substrates under both quasistatic and strong non-equilibrium transient conditions. In particular, the developed large-signal modelling scheme is demonstrated to be stable, i.e. to converge in both space and time, and to correlate well to a wide set of measurement data from over 20 different silicon-based substrates. The impact of each considered parameter, be it a material parameter (traps, doping, interface charge, etc.), an excitation parameter (signal amplitude, frequency, etc.), or an environment parameter (temperature, dimensions/layout of the structure, etc.), is not only well captured by the model, but beyond that the data trends can be fully ex, (FSA - Sciences de l'ingénieur) -- UCL, 2021

This work studies the effect of heat sink in the back-end of line (BEOL) on the self-heating (SH) parameters of transistors in a Fully Depleted Silicon-on-Insulator (FDSOI) technology. The RF characterization technique, which involves S-parameter measurements over a wide frequency range, is used to evaluate SH parameters. Two types of sink configurations in the BEOL are considered; one connected to the gate and the other left floating. We experimentally demonstrate that gate-connected heat sink allows for a reduced self-heating in 22 nm FDSOI devices. Around 15% to 30% reduction in thermal resistance is observed for the gate-connected heat sink in comparison to the floating sink

The reduction of substrate RF losses and nonlinearities is key to enable high-performance GaN-on-Si HEMT based RF front-end modules. In this paper, the impact of the epitaxial III-N buffer layers on substrate RF losses and harmonic distortion is studied experimentally using coplanar waveguide (CPW) structures. In contrast to a SiO2/Si stack, a strong hysteresis in the RF losses (quantified using effective resistivity (rho_eff) of the HEMT stack is observed when the chuck DC bias is swept. A comparative analysis of various material stacks suggests that the hysteresis originates from the large time constants (much larger than 1 s) associated with the traps in the III-N layers. Harmonic distortion, on the other hand, shows much weaker hysteresis effect than reff during chuck bias sweeps