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Field programmable gate arrays (FPGAs) use memory cells, primarily static random-access memory (SRAM) cells to implement field programmability for logic and interconnect, which is a preferable platform due to its high performance and low non-recurring engineering cost. To increase the logic density and the integration capability, modern FPGAs use ever advancing process technologies and smaller devices. However, smaller devices are more vulnerable to environmental upsets caused by high energy particle hits and internal noise, and may change their logic states as a result. Such an upset is called a "Soft Error"', which is recently acknowledged as the most critical reliability issue for FPGAs.In the contexts of system failure and circuit functional failure, this dissertation studies the effects of soft errors caused by environmental upsets of modern FPGA architectures and presents novel methods for soft error tolerance to improve FPGA robustness from system to circuit levels. This dissertation first presents a comprehensive soft error analysis framework for SRAM-based FPGAs. By using a stochastic soft error model, the soft error sensitivities toward functional failures of a design implemented on an FPGA are quantitatively identified. At the system level, a novel FPGA configuration memory (CRAM) soft error mitigation technique by Heterogeneous CRAM Scrubbing (HCS) is proposed. Next, at the circuit level, two in-place resynthesis techniques are proposed: In-Place Decomposition (IPD) for FPGA logic elements and In-Place inVersion (IPV) for FPGA interconnect components. In contrast to existing redundancy techniques, the proposed techniques are attractive because they do not change circuit global placement and routing and hence, have negligible cost on performance, area, and design closure. Furthermore, a co-optimization algorithm leveraging the proposed IPV technique for soft error and leakage reduction is proposed. Finally, this dissertation also demonstrates validation of the IPV technique on an industrial FPGA.