103 results on '"Lillis, John"'
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2. Vertical Files in Midlands Academic Libraries.
3. A layout-level logic restructuring framework for LUT-based FPGAs
4. RBI: Simultaneous placement and routing optimization technique
5. An approach to placement-coupled logic replication
6. Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages
7. Buffered Steiner trees for difficult instances
8. Generalized Buffer Insertion
9. Generalized Buffer Insertion
10. Data flow partitioning with clock period and latency constraints
11. Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation
12. Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming
13. A Method for improved final placement employing branch-and-bound with hierarchical placement encoding and tightened bounds
14. A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs
15. A framework for layout-level logic restructuring
16. Repeater insertion for concurrent setup and hold time violations with power-delay trade-off
17. Trunk Decomposition Based Global Routing Optimization
18. Techniques for improved placement-coupled logic replication
19. A study of tighter lower bounds in LP relaxation based placement
20. An LP-based methodology for improved timing-driven placement
21. An approach to placement-coupled logic replication
22. Session details: Clock routing and buffering
23. Timing optimization of FPGA placements by logic replication
24. Session details: Technology mapping, buffering, and bus design
25. Trunk decomposition based global routing optimization.
26. A fast algorithm for context-aware buffer insertion
27. Relaxation and Clustering in a Local Search Framework: Application to Linear Placement
28. S-Tree
29. An LP-based methodology for improved timing-driven placement.
30. An approach to placement-coupled logic replication.
31. Timing optimization of FPGA placements by logic replication.
32. S-Tree.
33. Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages.
34. Mongrel.
35. A fast algorithm for context-aware buffer insertion.
36. A fast algorithm for context-aware buffer insertion
37. Relaxation and clustering in a local search framework
38. Timing driven maze routing
39. Timing optimization for multisource nets: characterization and optimal repeater insertion
40. REVIEWS
41. Table-lookup methods for improved performance-driven routing
42. Timing optimization for multi-source nets
43. New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
44. New spectral linear placement and clustering approach
45. REVIEWS
46. Relaxation and clustering in a local search framework.
47. Linear decomposition algorithm for VLSI design applications.
48. Table-lookup methods for improved performance-driven routing.
49. Timing optimization for multi-source nets.
50. New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing.
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