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The low-density parity-check (LDPC) codes are by far the best error-correction codes discovered till date, providing exceptional performances that verge on the theoretical boundary, otherwise known as the Shannon limit. Yet, in the process of manipulating its enticing features, modern LDPC applications, explicitly the non-volatile memories (NVM), are more often than not encumbered by its very decoding mechanism of recursive nature, which fuels the capacity-approaching performances of the LDPC codes. This thesis therefore demonstrates numerous propositions pertaining to cost-effective high-throughput implementation of the LDPC decoders on field-programmable gate-array (FPGA) hardware, alongside ingenious techniques to compensate for certain performance loopholes in LDPC decoding. Moreover, the possibility and potential of amalgamating two or more of the proposed works have been accomplished and substantiated in this thesis, rendering a concerted effect of high-throughput decoding and low-complexity realization while retaining outstanding decoding performances. Doctor of Philosophy (EEE)