Search

Hardware acceleration of deep learning using analog non-volatile memory (NVM) requires large arrays with high device yield, high accuracy Multiply-ACcumulate (MAC) operations, and routing frameworks for implementing arbitrary deep neural network (DNN) topologies. In this article, we present a 14-nm test-chip for Analog AI inference--it contains multiple arrays of phase change memory (PCM)-devices, each array capable of storing 512 x 512 unique DNN weights and executing massively parallel MAC operations at the location of the data. DNN excitations are transported across the chip using a duration representation on a parallel and reconfigurable 2-D mesh. To accurately transfer inference models to the chip, we describe a closed-loop tuning (CLT) algorithm that programs the four PCM conductances in each weight, achieving

We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out from RO environments. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.

In a previous study [1], the authors have investigated stacked silicon microcoolers and quantified their thermal performance envelope in a separable format where the microcooler is attached to an electronic package lid with an intervening TIM2. In this study, we expand the previous study by integrating the stacked microcoolers into an electronic package, i.e., by removing the lid and the TIM2.A summary of thermal resistance and pressure drop experimental data spanning a wide range of fluid flow rates is presented. Additionally, numerical modeling using FEA/CFD models is conducted and the results compared to the experimental data.Results reveal that the thermal performance of the integrated microcoolers is ~ 30% superior that of the separated microcoolers. The numerical model results accurately predict the experimental data to within 20%. Directions for future thermal performance improvements using multiple inlet/outlet ports and varying the number of cooler stacks are identified using the numerical models.

We introduce a new packaging technology termed as Direct Bonded Heterogeneous Integration (DBHi) where a Si-bridge is directly bonded to and in between processor chips using Cu pillars, allowing high-bandwidth low-latency low-power communication between the chips. The DBHi package structure, test vehicle design, and bond and assembly details are first described. The test vehicle package consists of chips with standard interconnect pitch where they join to a laminate chip-carrier and fine-pitch pads in the region where the chips joins to a bridge. The bridge has Cu pillars correspondingly mating to the pads on the chips. The bond and assembly sequence starts with first joining the silicon chips and bridge using a thermocompression bonding process followed by a mass reflow join of the chips to the laminate. The assembly is then underfilled and capped using specialized techniques. Mechanical modeling was extensively used to simulate the DBHi structure and assembly process to allow material selection and reliability prediction. The mechanical models were calibrated using warpage measurements. The stress/strain reliability metrics of the DBHi package are compared to a non-bridge package of the same dimensions. Results show that the main focus should be directed towards ensuring a robust assembly process as the standard reliability stress/strain metrics of the DBHi package are very similar to a non-bridge package. Thermal measurements using chip heaters and temperature sensors were conducted to calibrate a numerical thermal model of the DBHi package. The thermal model was exercised to show the relation between the allowable chip and bridge power densities for the particular package size and cooling conditions. DBHi test packages were created using the best-known assembly process and then measured for continuity performance. A variety of inter- and intra-bridge daisy chain nets were incorporated into the test vehicle for continuity measurements. Post-assembly continuity measurements demonstrated a robust assembly process for multiple rounds of assembly. Reliability performance was demonstrated using standard JEDEC tests of thermal cycling, aging, and temperature/humidity.

The recently introduced Direct Bonded Heterogeneous Integration (DBHi) Si bridge technology has chips connected by a bridge housed inside a cavity or trench that is precisely machined in the chip-carrier laminate. The size, thickness, and placement centrality of the bridge are critical parameters that are necessary to prevent interference with the laminate substrate trench. In this study, we compared laser and saw dicing processes for the DBHi bridge technology. Different laser dicing recipes are developed and optimized. The laser and saw dicing process are compared for dimensional tolerances, edge quality, and die strength of the bridge chips. The die strength is affected by the edge defects on the top and bottom surfaces adjacent to the edges and is measured using a three-point bend fixture in a Universal Testing Machine (UTM). The laser dicing process is improved to equalize the die strength at both the surfaces as well as to achieve equal or higher die strength than blade dicing specifically for the thinner wafer thicknesses.

With increasing processing capability and power consumption in multi-layered micro-electronic packages, efficient thermal management and structural integrity continue to remain crucial factors for ensuring package reliability. Effective and simple to implement analytical methods for temperature and warpage prediction are important tools to predict the thermo-mechanical performance of a package. While many existing analytical thermal models predict exact or approximate solutions [1], [2], they are computationally expensive for non-uniform power distributions and do not account for the effect of thermal warpage on the package thermal resistances and the temperature distribution. Similarly, existing methodologies for calculating the warpage or thermal stresses in bi- and multi-layer strip [3], [4] do not consider non-uniform power distribution on the chip surface.This paper presents an analytical solution for the temperature distribution in a multilayer chip-on-spreader package, combining the thermal warpage of the chip and package with the imposed uniform and non-uniform power distributions on the chip. An analytical solution is developed to calculate the warpage and the radius of curvature for a multilayer unlidded package as a result of mismatch in the thermal expansion of the package components as its temperature varies. The model is verified against Timoshenko’s model for two layers and is found to be a match. The temperature distribution on the chip is calculated using an analytical method for an unwarped package [5] where the linear superposition principle is applied to an exact solution of heat transfer in the spreader, coupled with 1D heat conduction from the chip and the thermal interface material (TIM) to the spreader. The two methods are solved implicitly until a converged solution is reached. The temperature distribution and the warpage results are presented for 10 by 10 grid uniform and non-uniform power maps applied to the chip. The model predicts a significant change in the temperature distribution as a result of package warpage. The results are also reported for a 60 by 60 grid non-uniform power map representative of power dissipation in a server chip. A comparison between the analytical model and the numerical results is also presented and are found to be in good agreement.

Using silicon for microcooler fabrication is advantageous over metals as it can be micromachined for smaller fin wall and channel width dimensions, increasing the thermal heat transfer coefficient [1], [2]. Since the fin height is limited by the wafer thickness, multiple microcoolers are stacked to increase the total fin height to enhance the heat transfer from a chip. Stacked silicon microcoolers have been previously designed, fabricated, and characterized for thermal performance [3].In a multi-core processor package, the power density across the chip surface is highly nonuniform; the power density in the cores can be 4-6 times that outside the cores. In this study, we explore a variety of non-uniform power distributions on the chip surface for characterizing the thermal performance of integrated stacked silicon microcoolers. An array of individually controllable heaters, present on the test chip, is used to generate heating patterns corresponding to high-power computing cores. The thermal resistance to the heat transfer across the microcooler and the pressure drop in the water flow across the microcooler are characterized as a function of the flow rate. The cooling power limits of such high-power computing core maps are also defined. Finally, a numerical analysis is performed for the non-uniform power dissipation cases to validate the experimental results.

The recently introduced Direct Bonded Heterogeneous Integration (DBHi) Si bridge technology [1] consists of chips directly connected by a bridge chip though Cu pillars, enabling high speed and high band-width communication between CPUs, GPUs and memory chips. The bridge chip resides in a cavity machined in the laminate chip carrier. The remaining structure of the DBHi package is similar to a standard flip-chip package. In this study, we focus on the thermal characterization of the DBHi package using measurements and simulations. We determine how much heat generation is allowed for a bridge chip using a conventional cooling solution from the chip top side. The thermal measurements are conducted using a DBHi package with thermal test chips containing heaters and temperature sensors. The chips are heated by supplying power to the heaters and the temperatures on the chips are measured using resistance temperature devices. We then build a simulation model which is calibrated with the thermal measurement results by adjusting the heat transfer coefficient applied to the package lid top. The model comprises two chips, a bridge chip, interconnects between the chips and the bridge, interconnects between the two large chips and a laminate, a Thermal Interface Material (TIM) and a heat-spreader (a lid). Based on this simulation model, it is examined how much heat generation is allowed for a bridge chip when its maximum temperature is to remain below 75 °C (with an ambient = 40 °C). For example, it is simulated that when each chip generates 100 W (total 200 W for two chips), 26.5 W of heat generation is allowed for a bridge chip. We also consider potential cooling solutions from the laminate side.

Ring Oscillators (ROs) are used for yield learning during the research phase of a CMO technology. We performed cross-sections and showed that the open and short defects are in the middle of line (MOL) gate structures. The defects which are related to MOL or prior processes, as well as the design and density, will be discussed in the paper.

Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a factor of two improvement in comparison to optical or scanning electron microscope based processes. This paper provides an additional update on this project. The study is about a GDS based process developed to simplify the complicated workflow for examining discrete electrical failures. The results of this study indicated that the recipe prototype developed on a test structure had a unique feature that consisted of an approximately 45nm by 200nm Cu line segment. Executing the prototype recipe on a wafer at the same process point fabricated 6 months after the original wafer yielded four identical successful samples of about 30nm sample thickness. This technique can thus be extended to large 2D arrays of small structures.

Ring oscillators (ROs) are used for yield learning during the research phase of a CMOS technology generation. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.

We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out from RO environments.