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Matrix-Vector Multiplications (MVMs) represent a heavy workload for both training and inference in Deep Neural Networks (DNNs) applications. Analog In-memory Computing (AIMC) systems based on Phase Change Memory (PCM) has been shown to be a valid competitor to enhance the energy efficiency of DNN accelerators. Although DNNs are quite resilient to computation inaccuracies, PCM non-idealities could strongly affect MVM operations precision, and thus the accuracy of DNNs. In this paper, a combined hardware and software solution to mitigate the impact of PCM non-idealities is presented. The drift of PCM cells conductance is compensated at the circuit level through the introduction of a conductance ratio at the core of the MVM computation. A model of the behaviour of PCM cells is employed to develop a device-aware training for DNNs and the accuracy is estimated in a CIFAR-10 classification task. This work is supported by a PCM-based AIMC prototype, designed in a 90-nm STMicroelectronics technology, and conceived to perform Multiply-and-Accumulate (MAC) computations, which are the kernel of MVMs. Results show that the MAC computation accuracy is around 95% even under the effect of cells drift. The use of a device-aware DNN training makes the networks less sensitive to weight variability, with a 15% increase in classification accuracy over a conventionally-trained Lenet-5 DNN, and a 36% gain when drift compensation is applied.

Smart devices for structural health monitoring provide edge computing capabilities to reduce wireless transmission and, thus, power consumption. Although effective algorithms have been proposed in the last few decades, traditional microcontrollers require heavy data flow between the memory and the central processing unit that involves a considerable fraction of the total energy consumption. Phase change memory has recently emerged as an attractive solution in the field of resistive non-volatile memory for analog in-memory computing, which is a valid approach to avoid data being conveyed among distinct elaboration units. However, it has never been envisaged in structural health monitoring applications. As this technology is still in an embryonic state, several challenges related to nonlinearities and nonidealities of the memory elements and the energy expenditure related to the memory reprogramming process may undermine its usage. In this paper, the application of a novel identification approach for civil infrastructures is investigated using phase change memories. The main computational core of the presented algorithm, consisting of 1-dimensional convolutions, is particularly suitable for implementations involving analog in-memory computing, thus showing the great potential of this technology for structural health monitoring applications. The test unit is an embedded phase change memory provided by STMicroelectronics and designed in 90-nm smart power bipolar complementary metal-oxide-semiconductor (CMOS)-double-diffused metal-oxide-semiconductor (DMOS) technology with a Ge-rich Ge-Sb-Te alloy for automotive applications. Experimental results obtained for a viaduct of an Italian motorway support the efficacy of the method. Moreover, the influence of nonidealities on the outcomes of damage identification based on both dynamic and quasi-static structural parameters is examined.

This letter presents a 2-Mb embedded phase change memory (ePCM) macrocell designed in 90-nm BJT-CMOS-DMOS (BCD) technology able to address the next generation of automotive and smart-power products exploiting an ePCM cell based on a Ge-rich chalcogenide alloy. The optimized memory allows 16-ns random access time and 5-Mbit/s write throughput from −40 °C to 175 °C, with 100 kcycle endurance. The sense amplifier, the programming circuitry, and the data processing logic able to meet automotive requirements are described. The silicon results are provided.

In this paper, a thorough characterization of phase-change memory (PCM) cells was carried out, aimed at evaluating and optimizing their performance as enabling devices for analog in-memory computing (AIMC) applications. Exploiting the features of programming pulses, we discuss strategies to reduce undesired phenomena that afflict PCM cells and are particularly harmful in analog computations, such as low-frequency noise, time drift, and cell-to-cell variability of the conductance. The test vehicle is an embedded PCM (ePCM) provided by STMicroelectronics and designed in 90-nm smart power BCD technology with a Ge-rich Ge-Sb-Te (GST) alloy for automotive applications. On the basis of the results of the characterization of a large number of cells, we propose an iterative algorithm to allow multi-level cell conductance programming, and its performances for AIMC applications are discussed. Results for a group of 512 cells programmed with four different conductance levels are presented, showing an initial conductance spread under 6%, relative current noise less than 9% in most cases, and a relative conductance drift of 15% in the worst case after 14 h from the application of the programming sequence.

A low power and low voltage sense amplifier is presented in this brief for emerging nonvolatile memories such as Phase Change Memory (PCM), Resistive RAM (ReRAM) and Spin Transfer Torque Magnetic RAM (STT-MRAM). These memories use a special Alloy element, which is modeled as variable resistor. During programmed (RSET) and erased (SET) state, these elements exhibit large distribution in resistance value. This work presents a fast, reliable, power and area efficient sense amplifier in 110nm BCD technology with embedded PCM option. The proposed sense amplifier is able to sense sub $\mu$A current difference between memory cell and reference current at 1. 2V supply voltage and can operate at entire automotive grade temperature range from -40°C to 175°C.

In this paper, a row decoder architecture is discussed, that is designed using low voltage transistors, targeting fast word-line charging. Total Read timings in any memory can be divided into two parts: Word-line (WL) capacitive load charging time and Sense amplifier reaction time. Word-Line charging time is decided by WL-driver, Row-decoder and pre-decoder stages, architecture and type of transistor used in circuits. Here, a Row-decoder architecture (specifically used for Phase Change Memories) is presented that can help in achieving fast WL charging during Read operation and during Modify operation, it can bias WL at high voltage without compromising the reliability. In this architecture, Low voltage transistors are used with separated low voltage and high voltage paths for Memory Read and Modify operations. All devices are operated in their safe operating area (SOA) ensuring reliability of circuit.

In the frame of power electronics applications, the request for smart and reconfigurable devices is pushing integration technologies in the direction of embedded systems. In this scenario, microcontrollers play a key role, and the availability of embedded non-volatile memory (eNVM) to store the microcontroller code has become crucial to enable real-time customization and increase system flexibility. Among emerging NVMs, phase change technology is becoming a very attractive solution for the development of applications for smart power and automotive markets. In this paper, a 32-KB embedded phase change memory (ePCM) designed and manufactured in 0.11- $\mu \text{m}$ smart power BCD technology with a specifically optimized Ge-rich Ge-Sb-Te (GST) alloy (supply voltage = 1.8 V) is presented. Thanks to the use of a differential sensing scheme, the proposed ePCM features 18-ns random access time with improved robustness against resistance drift. The word modify time under 32-cell programming parallelism was kept as low as 20 $\mu \text{s}$ , thanks to enhanced programming circuits. The size of the 32-KB eNVM is about 0.7 mm2.

This paper presents a current DAC based configurable wide output voltage range Low Drop-Out (LDO) regulator. This LDO uses a multi-supply operational amplifier architecture that uses low supply voltage (1.8V) for input stage in differential amplifier and high supply voltage (5V) for output stage. A nested miller compensation combined with buffer compensation scheme is presented that provides a fast transient response and full range AC stability from 0 to 100mA load current for an output capacitive load of 50pF using compensation capacitor of 5pF. LDO output is configurable using internal current based digital to analog converter (DAC) and output voltage ranges from 2.3V to 5.5V with a step of 107mV. Total loop gain of LDO is 127dB at DC and PSRR is -40dB at 1MHz frequency for no current load condition. Presented LDO is designed in 110nm STMicroelectronics BCD9s technology; consuming 30µA of total ground current (without current DAC).

The demand for more and more efficient management of power systems is causing BCD technologies to move forward in the integration of additional digital functions, and the use of microcontrollers in products has become a common practice. In this perspective, the introduction of an embedded nonvolatile memory (eNVM) to store the microcontroller code has become important to enable software customization. In this paper, a 32 KB embedded Phase Change Memory (ePCM) designed and manufactured in 0.11 μm Smart Power BCD technology with a specifically optimized Ge-rich Ge-Sb-Te alloy (supply voltage = 1.8 V) is presented. The ePCM features 18 ns random access time and robustness against resistance drift thanks to the used differential sensing scheme and 20 ss word modify time with 32-cell programming parallelism thanks to enhanced programming circuits. The 32 KB eNVM size is 0.7 mm2.

Several recent works have shown the advantages of using phase-change memory (PCM) in developing brain-inspired computing approaches. In particular, PCM cells have been applied to the direct computation of matrix-vector multiplications in the analog domain. However, the intrinsic nonlinearity of these cells with respect to the applied voltage is detrimental. In this paper we consider a PCM array as the encoder in a Compressed Sensing (CS) acquisition system, and investigate the effect of the non-linearity of the cells. We introduce a CS decoding strategy that is able to compensate for PCM nonlinearities by means of an iterative approach. At each step, the current signal estimate is used to approximate the average behaviour of the PCM cells used in the encoder. Monte Carlo simulations relying on a PCM model extracted from an STMicrolectronics 90 nm BCD chip validate the performance of the algorithm with various degrees of nonlinearities, showing up to 35 dB increase in median performance as compared to standard decoding procedures.