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Fan-Out enables new heterogeneous packaging concepts where chips are embedded in an electronic mold compound (EMC) package with ultra-small footprint. These multi-chip systems demand a high routing density in the redistribution layer (RDL) which is realized by fine copper features with line and space structures in the dimension down to 2 μm, establishing electrical interconnects between the chips across different substrate materials (e.g. silicon chips and mold-filled gaps). The copper lines undergo high mechanical stress due different thermal expansion coefficients of the used materials. Numerous papers investigated reliability topics only focusing on properties of the polymer in the redistribution layer and the solder ball material, but the influence of the mechanical properties of electroplated copper has been a minor topic so far [1] [2] [3].With feature sizes and thicknesses of about 2 μm, these structures are in the range of copper grain size with the result that different grain structures become more important. Also, the material suppliers start to tune galvanic copper baths to generate e.g. twinned copper structures with mechanically superior behavior. Characterizing these fine structures at that scale is challenging because the properties could be different compared to macro samples. This work presents an on-wafer characterization method of copper features down to 2 μm with a newly designed wafer scale micro tensile test. This concept allows a test integration in the fab process flow. The elongation at break and the tensile strength of ultra fine line copper lines are measured by the tensile loading. The results are compared with macro scale tensile tests.

The technological evolution regarding multi-chip integrated Fan-Out packages and chip scale packages (CSPs) with high amounts of I/O demands for even higher routing densities. Conventional used technologies and materials like mask aligner and photosensitive polymers used for semi additive process (SAP) in the BEOL have reached its limits to push the resolution down to two um. New materials and technologies are necessary to overcome these limits. As the routing density increases, so does the reliability requirements. The electrochemical migration between Cu lines cannot be neglected and need to be analyzed as the distance between the Cu lines is decreasing. A new approach for fine-line multi redistribution layers (RDL) realized by an excimer laser dual damascene process was presented in the past, using laser ablation and Cu chemical mechanical planarization (CMP) to realize embedded Cu lines. This approach has several advantages regarding the processing but one of the most important characteristics of the damascene approach is the improved electrochemical migration behavior. The Cu lines are partially cladded by the Ti part of the seed layer due to the way of processing. The Ti acts as a barrier layer and inhibits the Cu migration into the surrounding polymer. RDL structures realized by conventional SAP have Ti only under and not between the Cu lines. In this study different test samples with interdigital structures (resp. interdigital capacitor IDC) with five um line and space width (L/S) were realized to analyze the electrochemical migration behavior between the fingers of the IDC. The samples were realized by SAP and by the excimer laser damascene process and were subsequently tested by the temperature humidity bias (THB) test resp. biased High Accelerated Stress Test (bHAST). With the help of this work, we were able to compare the reliability of both process variants and to demonstrate and prove the reliability of embedded copper lines realized by the excimer laser damascene process.

Multi-chip integrated Fan-Out packages and high I/O CSPs demands for higher routing density on wafer level. Due to that, the classical mask aligner lithography and photosensitive thin-film polymers used for BEOL reach its limits and new technologies and materials are necessary to generate lines and space down to two μm. These multi-metal layers set also higher demands on the mechanical properties of the materials. This paper presents a new excimer laser dual damascene process for ultra-fine routing for BEOL. Various materials like low cure temperature polyimide, BCB and 15-μm thick dry-film ABF material are structured by using an excimer laser stepper with a reticle mask to realize feature size below four μm with a high throughput. Micro-vias with a diameter below five μm are realized with high aspect ratio, which overcome the photolithographic limitations of the common used photosensitive thin-film polymers. The laser structuring allows to use innovative dielectric materials for WLP with optimized mechanical and electrical parameters for example inorganic filled polymers like dry-film ABF materials, which do not have to be photosensitive. The ablations depth per laser pulse and the cross-section of the ablated structures in dependence of the ablation parameters was investigated. The depth of embedded lines was set by number of pulses aside of integrated micro-vias. The lines and micro-vias were metallized with copper by galvanic process and the following CMP step removes the copper outside the ablated structures. The CMP removes only the copper and the metal of the seed-layer, which has the functions of an adhesion and barrier layer, stays intact. The under-etching of the conventional wet etch seed layer removal is a major problem for the fine line structures realized by the Laser Dual Damascene process. Due to that, the removal of the seed layer (usually titan) was investigated and it could be shown, that this layer can be removed by the excimer laser system. The stepper like system allows a sub-micron alignment accuracy with no need of a capture pad of the embedded lines. Test structures have been designed and fabricated with lines and spaces below 10 μm to demonstrate the dense multi-layer routing capability where the excellent reliability can be proven by air to air thermal cycling (from −55°C up to 125°C), current leakage and electro migration test.

Glasses are homogeneous, many glasses have excellent dielectric properties at GHz frequencies and some have thermal expansions (CTE) which are close to silicon. Ultrathin glasses (UTG) with thicknesses of 25 μm to 200 μm (0.001 to 0.0079 inch) offer numerous options for packaging, integration and co-processing in semiconductor manufacturing processes. We introduce SCHOTT UTG including paths to further improve their mechanical stability and strength. We use laser ablation in 50μm thick glass and show via fabrication with a potential of mass manufacturing with via diameters of 30μm, 38μm pitch and a position accuracy of +/− 1μm. The structures are metallized using sputtering and electroplating which leads to hermetic, tight conducting through glass-vias (TGV).

The Fan-Out Wafer Level Packaging (FOWLP) is one of the biggest impacts for the microelectronics packaging today. Main benefit is the high potential in significant package miniaturization by the substrate-less short interconnects, which are realized by thin film metallization directly on the embedded dies instead of wire bonding or flip chip - bumps. This allows a cost effective and robust generation of multi-chip packages for System in Package (SiP) solutions. The thickness of the FOWLP's which are in volume production is in the range of 300 to 400 um [1]. The stacking of FOWLP packages for higher integrations set demands for thinner packages. Main limitation for high volume production of packages below 300 um is the handling of the thin substrates during the processing and the assembly of thin and also warped packages. This paper presents an innovative concept (Hybrid Fan-Out - hFO) for generation and handling of thin FOWLP substrates. A fundamental process change is realized in the so called chip-first approach which enables packages with thickness down to 30 um and below. The mold-first approach based on the assembly of dies on a thermal release tape, which is followed by the embedding process. The epoxy mold compound (EMC) substrate with the embedded dies is released from the carrier by peeling of the TRT and the redistribution layer (RDL) is generated. For the new approach the dies are directly assembled on a glass carrier with a die adhesive. The temperature stable bond of the dies to the glass carrier enables a thinning and backside processing of the EMC / glass carrier stack. The embedded dies are coincidently thinned together the mold material with the benefit, that no thinned dies are demanded for generation of thin packages and simplifies the assembly process. A RDL process is applied on the backside, which stabilize the ultra-thin package. A ultra-fine routing layer could realized because the stiff glass carrier inhibits any EMC substrate deformation or length changes, like it is happen by cure shrinkage or humidity uptake. The RDL on the front side is generated after the release from the carrier. The symmetric build-up structure with an EMC core and a double sided RDL allows to increase the number of routing layers, which are demanded for shielding and supply layers for RF applications. FOWLP packages with a thickness down to 50 um are demonstrated in this paper.

Thin film polymers, like PI, PBO and BCB are used in every wafer level packaging device. The improvement of the reliability of wafer-level packages and chip I/Os consider the choice of the polymer, which is used as dielectric on the chip, as a minor point. Because the production lines are normally fixed on one polymer and the high investments to evaluate the processing of an alternative polymer formulation in combination with costly reliability test seems to be not attractive till today. But the increased demands of advanced WLP and 3-D-Integration, which includes thin chips, chips stacking and higher routing densities, leads to reaching the limits of the common used material system combinations. The demand of better polymer films becomes evident by the fact that dozens of “next generation polymers” have entered the marked in the last years, which are tailored to get higher mechanical toughness and electrical performance aside of a nearly unchanged resolution capacity. The challenge for new polymer formulation is the evaluation of the processing and the generation of a reliable material property data base, which set the basics for any benchmarking to the already used polymer materials. The processing evaluation is done typically by the material supplier or the fab himself, where no special equipment is needed. The material property generation is a quite more complex topic because you need special equipment and partly the material need to be free standing without any substrate. This is also a handling issue, if we talk about thin films in the range of 5 to 20μm. This paper presents the reliable thin film polymer properties characterization of mechanical and electrical values. The measurements of the mechanical properties include the estimation of parameters like young's modulus, tensile strength, elongation at break, coefficient of thermal expansion, stress and time-temperature related effects. The evident topic of warpage related impacts by “new generation polymers” will be presented and discussed. Measurement structures on wafer-level are developed for the estimation of the electrical parameters, which allows a high accuracy and a device relevant value estimation. Parameters like break down voltage, leakage current, dielectric constant, loss factor are measured related to frequencies by MIM and resonator structures. We demonstrate with analyzing of the time-dependent dielectric breakdown (TDDB) of thin film polymers that there is an exponential linkage between field strength and the time till the breakthrough occurs. The mechanical and electrical properties were also investigated related to aging effects, when the application is running on elevated temperature. We examine a degradation of the mechanical and electrical performance, which should be taken into account for the mechanical system reliability and also for impedance controlled HF-application. This paper present advanced material characterization of thin film polymers which gives a guideline for the decision of the polymer related to the demands of the application.

The demands of higher routing density on wafer level are driven by multi-chip integrated fan-out packages and high I/O CSPs. New technologies and materials are necessary to generate lines and spaces down to 2 µm. Multi-metal layers are necessary for the higher wiring effort on panel level packaging (PLP) for example to contact dies which are embedded together. This places higher demands on the mechanical properties of the materials that are used for the redistribution layer. This paper presents a new excimer laser-enabled dual damascene process for ultra-fine routing for BEOL which was developed in a joint project with SUSS MicroTec. In the project, various materials e.g. low temperature cure polyimide, BCB and dry-film ABF materials were structured by using an excimer laser stepper with a reticle mask to pattern feature sizes below 4 µm with a high throughput. Micro-vias with a diameter below 5 µm were ablated with an aspect ratios up to 4 which is exceeding the photolithographic resolution limits of the established photosensitive thin-film polymers. The laser structuring allows the usage of innovative dielectric materials for WLPs/PLPs with optimized mechanical and electrical parameters, for example polymers with inorganic fillers like dry-film ABF material. Also, the ablations depth per laser pulse was investigated. The ablated lines and micro-vias were metallized by applying a galvanic process and CMP. The stepper-like system allows a sub-micron alignment accuracy with no need of a capture pad in the redistribution layers. Test multi-layer structures have been designed and fabricated with lines and spaces below 10 µm to demonstrate the dense routing capability with an excellent reliability which was verified by air-to-air thermal cycling (from -55 °C up to 125 °C).

Glass is well established as wafer or panel substrate for applications like capping of image sensors or as low loss carrier for integrated passive devices. Glass substrates with higher functionality becomes more attractive for the advanced packaging due the improvement of glass processing and the increased implementation of photonic packaging which is demanded for higher data transfer rates. The through glass vias are therefore essential for the SiP and 3-D integration.

Thin film polymers play an essential role in system integration. The mechanical properties of the polymers are crucial for 3-D-Integration and advanced WLP because with the thinning of the silicon wafers, i.e. chips to less than 150 μm, the influence of the polymer layers gets an increasing impact on the mechanical stability of the electronic device. Next generation polymers have entered the market which are tailored to reach the further optimized mechanical property parameter set. This paper will give a guideline for the choice of the optimal polymer based on the demands of the application in relation to the material properties. The main material properties for high reliability are the Young's modulus, tensile strength, elongation at break and coefficient of thermal expansion. Aside of the material properties of the polymer the interaction of the polymer layer with the substrate is important. The material mismatch causes for example warpage and material cracking; the main impact factor being the residual stress in the layers in relation to the fracture toughness of the material and the interface. The warpage is an issue for the processing and the assembly process. The focus of our investigation is on properties of polymers on silicon substrates. The development of stresses in the polymer layers is measured and analyzed for different polymers (BCB, PI, PBO). The residual stress in a thin polymer film is measured by the warpage of the substrate in relation to different temperatures depending on the application. The estimation of stress-temperature behavior allows to develop processing concepts for a stress reduction being essential for 3-D integration. The generated stress drives cracking which leads to the effect that the impact of the forces should be taken into account for the quantification of the fracture toughness. The relation between the stress as the driving force and the fracture toughness are further discussed in details. A comprehensive study of the mechanical polymer properties is essential for high reliable devices.

Polymeric coatings such as polyurethanes, acrylic, epoxies and silicones have been used for over 40 years to protect printed wiring boards (PWB) from moisture, handling and environmental influences. Special semiconductor grade polymers have been developed for chip passivation layers. Polyimide became the standard passivation layer for memory chips and other devices needing surface protection for handling and testing procedures. Photosensitive resins have been developed to reduce processing costs. Thin film polymers are used widely in the area of electronic packaging and as an interlayer dielectric (ILD) in nearly every electronic device. Typical layer thickness ranges from 5 μm up to 15 μm. These polymers films should be temperature stable up to range of 150°C (permanent), and for a short time up to 250°C and higher, depending on the soldering process of the components. This is the reason to use thermoset polymers in most cases. The coating process is the spin-coating technology. Spray coating and other techniques are only niche processes. The polymer supplied by the chemical company is a so-called pre-cursor consisting of a partially polymerized polymer in an organic solvent. Nearly all of the thin film polymers need a polymerization step, which is done in most cases by a thermal process after the deposition on the wafer. Polymerization changes the pre-polymer into a long-term stable and much more inherent polymerized dielectric layer. The polymerization process is generally called the cure or cure step of the process. But the definition “cure” does not mean in every case a fully finished polymerization reaction. Also partly cured polymer films are possible and becoming important if multiple layers have to be deposited. Partly polymerized layers have better adhesion to the following layer compared to fully cured ones. To get something more precise the following definitions have been used: partly cured or soft cured polymers for a 60 – 80 degree of polymerization, and full cured or hard cured for a complete polymerized layer.