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45 results on '"Matsuura, Munehiro"'

1. An Architecture for IPv6 Lookup Using Parallel Index Generation Units

Author

Nakahara, Hiroki, Sasao, Tsutomu, Matsuura, Munehiro, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Brisk, Philip, editor, de Figueiredo Coutinho, José Gabriel, editor, and Diniz, Pedro C., editor

Published
2013
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2. A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU

Author

Nakahara, Hiroki, Sasao, Tsutomu, Matsuura, Munehiro, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Choy, Oliver C. S., editor, Cheung, Ray C. C., editor, Athanas, Peter, editor, and Sano, Kentaro, editor

Published
2012
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3. A Regular Expression Matching Circuit Based on a Decomposed Automaton

Author

Nakahara, Hiroki, Sasao, Tsutomu, Matsuura, Munehiro, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Koch, Andreas, editor, Krishnamurthy, Ram, editor, McAllister, John, editor, Woods, Roger, editor, and El-Ghazawi, Tarek, editor

Published
2011
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4. A Parallel Branching Program Machine for Emulation of Sequential Circuits

Author

Nakahara, Hiroki, Sasao, Tsutomu, Matsuura, Munehiro, Kawamura, Yoshifumi, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Becker, Jürgen, editor, Woods, Roger, editor, Athanas, Peter, editor, and Morgan, Fearghal, editor

Published
2009
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9. Programmable logic device with an 8-stage cascade of 64K-bit asynchronous SRAMs

Author

Nakamura, Kazuyuki, Sasao, Tsutomu, Matsuura, Munehiro, Tanaka, Katsumasa, Yoshizumi, Kenichi, Qin, Hui, and Iguchi, Yukihiro

Subjects
Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, Hardware_ARITHMETICANDLOGICSTRUCTURES, Hardware_LOGICDESIGN
Abstract

The first implementation of a new programmable logic device using LUT(Look-Up Table) cascade architecture is developed in 0.35um CMOS logic process. Eight 64Kb asynchronous SRAMs are simply connected to form an LUT cascade with a few additional circuits. Benchmark results show that it has a competitive performance to FPGAs., IEEE Symposium on Low-Power and High-Speed Chips (Cool Chips VIII), April 22-25, 2005, Yokohama, Japan

Published
2005

14. Bi-partition of shared binary decision diagrams

Author

Sasao, Tsutomu, Iguchi, Yukihiro, Matsuura, Munehiro, Butler, Jon T., and Department of Electrical and Computer Engineering

Subjects
SBDD, decomposition, multiple-output function, Shared binary decision diagram, bi-partition
Abstract

IEICE Transactions on Fundamentals of Electronics, Vol.E85-A, No.12, Dec. 2002, pp.2693-2700. This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted. A shared binary decision diagram (SBDD) represents a multiple-output function, where nodes are shared among BDDs representing the various outputs. A partitioned SBDD consists of two or more SBDDs that share nodes. The separate SBDDs are optimized independently, often resulting in a reduction in the number of nodes over a single SBDD. We show a method for partitioning a single SBDD into two parts that reduces the node count. Amoung the benchmark functions tested, a node reduction of up to 23% is realized.

Published
2001

37. Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition.

Author

Nakahara, Hiroki, Sasao, Tsutomu, and Matsuura, Munehiro

Abstract

Binary decision diagrams representing complex logic circuits require a large number of nodes. This paper shows a new method to represent logic circuits using multiple decision diagrams. First, a given logic circuit is converted into a direct acyclic graph~(DAG). Then, the DAG is decomposed into clusters. Next, clusters are represented by multi-terminal binary decision diagrams for characteristic function~(decomposed MTBDDs for CF). It represents a logic circuit more compactly than the conventional MTBDD for CF. Finally, the decomposed MTBDDs for CF are converted into the multi-terminal multi-valued decision diagrams for CF~(decomposed MTMDDs for CF) to be stored in the given memory size. Also, the decomposed MTMDDs for CF is faster to evaluate than the conventional MTMDD for CF using the same memory size on a BDD machine. [ABSTRACT FROM PUBLISHER]

Published
2012
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45. Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions.

Author

Iguchi, Yukihiro, Sasao, Tsutomu, and Matsuura, Munehiro

Subjects
DIGITAL-to-analog converters, ARITHMETIC, DIGITAL signal processing, BINARY number system, LOGIC circuits, MATHEMATICAL logic
Abstract

In digital signal processing, radixes other than two are often used for high-speed computation. In the computation for finance, decimal numbers are used instead of binary numbers. In such cases, radix converters are necessary. This paper considers design methods for binary to q-nary converters. It introduces a new design technique based on weighted-sum (WS) functions. The method computes a WS function for each digit by an LUT cascade and a binary adder, then adds adjacent digits with q-nary adders. A 16-bit binary to decimal converter is designed to show the method. [ABSTRACT FROM AUTHOR]

Published
2007

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