158 results on '"Mercha, Abdelkarim"'
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2. Channel Length Dependence of PBTI in High-k First RMG Gate Stack Integration Scheme
3. Plasma Charging Damage in HK-First and HK-Last RMG NMOS Devices
4. Analytical extraction of small and large signal models for FinFET varactors
5. High-frequency noise performance of 60-nm gate-length FinFETs
6. The potential of FinFETs for analog and RF circuit applications
7. A two-dimensional model for interface coupling in triple-gate transistors
8. Double-gate finFETs as a CMOS technology downscaling option: An RF perspective
9. Planar bulk MOSFETs versus FinFETs: An analog/RF perspective
10. Analysis of 2-MeV electron-irradiation induced degradation in FD-SOI MOSFETs fabricated on ELTRAN and UNIBOND wafers
11. Effect of high-temperature electron irradiation in thin gate oxide FD-SOI n-MOSFETs
12. Cumulated charging mechanisms at gate processing in high-κ first planar NMOS devices
13. Critical discussion of the front-back gate coupling effect on the low-frequency noise in fully depleted SOI MOSFETs
14. Short-channel radiation effect in 60 MeV proton irradiated 0.13 [micro]m CMOS transistors
15. The 1/f(super 1.7) noise in submicron SOI MOSFETs with 2.5 nm nitrided gate oxide
16. Gate Stack Influence on GIFBE in nFinFETs
17. CMOS Compatible Anodization Process for Low Cost High Density Capacitors
18. Low-frequency Noise Analysis of the Impact of an LaO Cap Layer in HfSiON/Ta2C Gate Stack nMOSFETs
19. Influence of Proton Irradiation in Bulk and DTMOS Triple Gate FinFETs
20. Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond
21. Impact of Wire Geometry on Interconnect RC and Circuit Delay
22. Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
23. Architectural strategies in standard-cell design for the 7 nm and beyond technology node
24. A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs
25. A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS
26. Impact of fin shape variability on device performance towards 10nm node
27. Modeling FinFET metal gate stack resistance for 14nm node and beyond
28. Impact of device and interconnect process variability on clock distribution
29. Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era
30. Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
31. Variability of quadruple-patterning interconnect processes
32. Maintaining Moore’s law: enabling cost-friendly dimensional scaling
33. DTCO at N7 and beyond: patterning and electrical compromises and opportunities
34. Standard cell design in N7: EUV vs. immersion
35. Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node
36. In-line monitoring test structure for Charge-Based Capacitance Measurement (CBCM) with a start-stop self-pulsing circuit
37. Comparative study of a fully differential op amp in FinFET and planar technologies
38. The economic impact of EUV lithography on critical process modules
39. STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process
40. TEASE
41. The need for EUV lithography at advanced technology for sustainable wafer cost
42. (Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors
43. Low-Frequency Noise Assessment of CMOS Transistors with a Through-Silicon Via
44. 3D technology roadmap and status
45. Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
46. FinFET Mismatch in Subthreshold Region: Theory and Experiments
47. Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions
48. 3D integration: Circuit design, test, and reliability challenges
49. 45-nm Planar bulk-CMOS 23-GHz LNAs with high-Q above-IC inductors
50. Verifying thermal/thermo-mechanical behavior of a 3D stack - challenges and solutions
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