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We report a correlative analysis between corona oxide characterization of semiconductor (COCOS) and Kelvin probe force microscopy (KPFM) for the study of embedded silicon-oxide interfaces in the field of chemical and field-effect passivation. Analyzed parameters by these measurements are linked to different factors and specifically to defects density of embedded silicon-dielectric interfaces, surface band bending or the distribution of charges in the nearest surface volume.Furthermore, this COCOS-KPFM correlative analysis turns out to be a useful method to access to chemical and field-effect passivation. We confirm that it is possible to differentiate the influence of local band bending on sample passivation (i.e. field effect passivation) from the effects due to the local recombination rates (i.e. chemical passivation).The measurements were carried on five different passivation layers, precisely, 10.5 nm-thick SiO2, 50 nm-thick SiN, 7nm-thick Al2O3, 7 nm-thick HfO2 and double layer of 7 nm-thick Al2O3 below 53 nm-thick Ta2O5. This correlative analysis indicates that HfO2 present to be the best chemical passivation and SiN is the worst case in term of field effect passivation for p-type silicon. Additionally, we confirm that Ta2O5 layer on top of Al2O3 increase the defects density.

International audience; A clear comparison between Atomic Layer Deposition and Ion Implantation Si doping techniques is established. Comparable remnant polarization and coercive fields are obtained at lower Si content (%Si) for Ion Implantation, with a slight decrease of endurance performance. Switching signal engineering demonstrates a wide range of performance achievable with HfO2:Si ferroelectric layer.

International audience; HfO2 synthesized by atomic layer deposition (ALD) can be used as a passivation material for photodetectors. This paper shows a significant reduction of density of interface traps at the Si/SiO2 interface using ALD HfO2. This is explained by a chemical passivation effect due to presence of hydrogen from water used in the ALD process. Furthermore, ALD HfO2 layers appear negatively charged which generate an additional field effect passivation. The impact of the SiO2 underlayer is also discussed by comparing a chemical silicon oxide to a standard thermal silicon oxide. It is shown that chemical silicon oxide can act as a reservoir of hydrogen atoms which helps to reduce the density of defects close to the Si/SiO2 interface. This result demonstrates the importance of the surface preparation before the ALD of HfO2 in the passivation scheme. Finally, this work shows the correlation between negatively charged defects and Si–O–Hf bonds at the SiO2/HfO2 interface. A passivation stack composed of chemical oxide permits to reach both a low density of interface traps (∼1.0 × $10^{11}$ $cm^{−2}$$eV^{−1}$) and a negative charge density (∼−1.0 × $10^{11}$ $cm^{−2}$). This stack provides both chemical and field effect passivation of the silicon surface.

International audience; In this paper, we report the effect of high temperature annealing on the chemical and electronic structure of technologically relevant TiN/LaOx/HfSiON/SiON/Si gate stacks. Using medium energy ion scattering from the backside of the samples, a non-destructive compositional depth profile of La has been obtained, revealing the lanthanum diffusion in the SiON interface layer upon annealing. To complement this analysis, hard X-ray photoelectron spectroscopy with synchrotron radiation has been performed to investigate the chemical and electronic structure of the gate stacks. The results show clear changes in the Hf and Ti core level energy positions with respect to Si bulk, with changes in the thickness of the LaOx capping layer. We infer that La diffusion generates an internal electrical field at the La-silicate interface between HfSiON and SiON, and that its strength increases with the increase of LaOx thickness. These findings support the band alignment model based on a La-induced interfacial dipole.

Zirconium dioxide is a good candidate to reach the capacitance density of 40fF/μm² required for decoupling applications. Indeed zirconia has a promising dielectric constant of 47 in the tetragonal phase. However, pure tetragonal zirconia layers deposited by PEALD do not fulfill the reliability criteria. We thus stabilize zirconia by addition of different metals. Tantalum is alloyed with zirconia. Since Ta solubility in ZrO2 is low, an orthorhombic ternary compounds appears and reduce the global dielectric constant of the layer. We also alloy zirconium dioxide with germanium. At high Ge concentration ZrO2 layers remain amorphous even after post deposition annealing, with a reduced dielectric constant. However at lower germanium concentration zirconia layers crystallize in tetragonal phase with better electrical properties than pure ZrO2.

In this work, cells based on TiN/TaO x /TiN metal–insulator–metal structure, fabricated in a 65 nm complementary metal oxide semiconductor technology, are investigated in order to propose a good stack candidate for multiple time programmable (MTP) applications. Firstly, the oxide material thickness and stoichiometry are optimized to minimize the forming voltage and the RESET current. Programming energies of the devices under different current compliance during the SET operation and with different cell size are studied putting in evidence the filamentary mechanism. Very high speed and low voltage for the ON (SET) operation are demonstrated. High thermal stability up to 125 °C is demonstrated in the SET/RESET states of the device (with an R OFF /R ON ~ 100). Promising data retention exceeding 24 h at 250 °C is also shown. Finally, due to the stability of this device, the high potential of TaO x -based resistive random access memory for MTP applications is demonstrated.

This work is focused on the investigation of Au/high k/TiN stacks for Resistive Random Access Memories. A screening of high k oxides, commonly used in advanced metal gates, such as HfO2 and ZrO2, is proposed. These oxides were grown on TiN electrodes using Atomic Layer Deposition and Plasma Enhanced Atomic Layer Deposition. The morphological and structural properties of the films were studied as a function of deposition temperature, film thickness and/or annealing using Atomic Force Microscopy, Grazing Incidence X-ray Diffraction and Attenuated Total Reflectance. An amorphous to crystalline transformation was observed with thickness for HfO2 and ZrO2, with deposition temperature for HfO2 from 300 to 350 °C, and with annealing in N2 for 1 h at 400 °C for ZrO2. According to density measurements obtained using X-ray Reflectometry, HfO2 and ZrO2 are suspected to be stoichiometric whatever the thickness. The film stoichiometry was confirmed using X-ray Spectroscopy. Current–voltage measurements were performed on Au/high k/TiN, where Au and TiN are top and bottom electrodes, respectively. Whatever the high k material, the crystallization increases with thickness or/and temperature without any significant modification of the SET operation. The film annealing, which was proposed as an alternative way to crystallize ZrO2, may cause a modification of the interfaces, leading to a decrease of the switching performance.

Cet article est une revue de l’utilisation du depot par couches atomiques dans le secteur de la microelectronique, en termes d’elaboration de couches minces et de realisation de composants. Les applications, la chimie des precurseurs, les mecanismes de croissance ainsi que les differents type de reacteurs (avec ou sans assistance plasma) sont decrits.

A unique gate stack solution has been found in gate-first FDSOI to meet at the same time high performance, low leakage, V T centering and reliability criteria for NMOS and PMOS with T inv =12.5A and 14A, respectively. Trade-offs between those characteristics are highlighted in this paper through process knob variations, including the interfacial layer (IL) formation, the IL surface treatment and the drive-in anneal temperature. The path allowing the construction of both low-V T high speed logic, reaching 7.2ps/stg FO3 ring oscillator delay at V nom =0.8V, and high-V T low leakage SRAM, achieving 3pA/cell standby leakage at V nom =0.8V, is demonstrated through gate workfunction engineering and gate leakage optimization. On top of this result, 5 years BTI and 10 years TDDB reliability lifetime were qualified at V max =0.945V, 125°C.

This paper deals with the electrical and wideband frequency characterizations of metal-insulator-metal (MIM) capacitors integrating the medium-k material ZrO2. First, the in situ material electrical properties are characterized in a frequency range from dc up to 5 GHz by using a microstrip waveguide method. The loss tangent and the permittivity are extracted with frequencies up to 5 GHz. We then investigate the evolution with frequency of the electrical parameters, such as capacitance density, quality factor, temperature coefficient of capacitance, voltage coefficient of capacitance, and cut-off frequency for MIM capacitors which incorporate ZrO2 dielectric layers with thickness from 10 to 45 nm.

The Chemical Vapor Deposition growth mechanism of a hafnium silicate film deposited by means of the co-flow of two precursors, TDEAH (tetrakis-diethyl-amino-hafnium) and 4DMAS (tetrakis-dimethyl-amino-silane), is characterized. Typical growth kinetics demand that the deposition rate increases and the silicon concentration remain stable with increasing reactor pressure. Though the deposition rate follows the expected growth kinetics, the silicon concentration in the silicate does not and exhibits an abnormal increase with increasing reactor pressure. To understand this atypical behavior the formation of pure HfO 2 from TDEAH and pure SiO x from 4DMAS is first studied. Experimental results show that whereas the HfO 2 deposition is well behaved and fits a diffusion-based model defined by assuming diffusion of TDEAH through a boundary layer, the deposition of SiO x with 4DMAS requires Hf-O nucleation sites and self-saturates after a single Si―O monolayer is formed. Based on these observations, a model is developed for hafnium silicate formation. The Atomic Layer Deposition like behavior of 4DMAS decomposition results in a deposition rate and film stoichiometry that are weakly sensitive to the 4DMAS partial pressure, and instead are driven by the TDEAH reaction. Since TDEAH operates within a transport-limited regime, the deposition rate is insensitive to substrate temperature, and is only controlled by the TDEAH partial pressure and the gas phase kinematics, rendering the process robust and easily controllable with excellent reproducibility.

The MOSFET gate length reduction down to 32nm requires the introduction of a metal gate and a high-K dielectric as gate stack, both stable at high temperature. Here we use a nanometric layer of Lanthanum to shift the device threshold voltage from 500mV. Because this layer plays a key role in the device performance and strongly depends on its deposition process, we have compared two LaO"x deposition methods in terms of physical properties and influence on electrical NMOS device parameters. Chemical characterizations have shown a different oxidization state according to Lanthanum thickness deposited. It has been related to threshold voltage shift and gate leakage current variations on NMOS transistors. Furthermore mobility extractions have shown that Lanthanum is a cause of mobility degradation.

INTRODUCTION The aggressive scaling of metal-oxide-semiconductor field-effects transistors (MOSFETS) faces the challenge of metal gate (MG) and high-k (HK) dielectric integration to reduce power consumption [1]. Hf-based oxides and silicates, such as HfSiON, are considered as the most promising candidates for next-generation gate dielectrics, owing to their high permittivity, with a sufficiently wide band gap and a good thermal stability [2]. However, the control of the threshold voltage (Vth) for the advanced nFET and pFET devices is challenging [3]. In gate first approach, the incorporation of LaOx capping layer has been reported to provide Vth shift towards the nFET band edge, yielding the necessary decrease of the effective work function (EWF) of the gate [4]. The mechanism of this voltage shift is attributed to La-induced dipoles at the HK/Si interface [5]. For this reason, the location of LaOx capping layer within the gate stack is a key factor for optimizing the transistor Vth. So far, detailed studies of La-capped gate systems have been focused on HfO2/SiO2 stacks. In this work, we have investigated the impact of high temperature thermal annealing and LaOx capping layer on electronic structure and band discontinuity for TiN/LaOx/HfSiON/SiON/Si gate stacks by coupling hard X-ray photoelectron spectroscopy (HAXPES) with synchrotron radiation and capacitance versus voltage (CV) measurements.

In the pursuit of smaller and faster devices manufacture, integration of new materials exhibiting a high dielectric permittivity is going on to replace silicon oxide SiO2 in Metal/Insulator/Metal (MIM) capacitors and in Dynamic Random Access Memory (DRAM). Among these materials, the zirconium oxide, ZrO2, in its highest dielectric permittivity phase (the high temperature tetragonal one) is investigated. Atomic Layer Deposition (ALD) of out-of-equilibrium ZrO2 thin films in 3D architectures is explored using various approaches: evaluation of the zirconium gaseous precursor, influence of operating conditions, thermal behavior of the deposited films. Thermodynamic models are used to better understand the film growth.

The impact of the deposition of a TiN electrode on the high-k oxide HfO"2 has been investigated, focussing on the dielectric band gap. After the gate elaboration, a non-destructive approach combining Spectroscopic Ellipsometry (SE), Reflection Electron Energy Loss Spectroscopy (REELS) and X-ray Photoelectron Spectroscopy (XPS) was developed to probe the buried metal/high-k interface. The overall optical band gap is 5.9+/-0.1eV with no change after the metal gate deposition. A local reduction of 1eV is measured near the TiN layer, due to N diffusion at the interface creating N 2p states at the top of the HfO"2 valence band. Increased disorder and defects are identified in the high-k after gate elaboration by XPS, REELS and SE.

In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX (Buried Oxide) thicknesses with or without ground plane (GP). With a simple high-k/metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well suited for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk 45 nm technology in terms of variability and noise. A 0.499 μm2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1 V.

To face with the continuous integrated circuit densification, passive components size has to be reduced, particularly for RF and analog applications where lots of them are needed. A Metal-Insulator-Metal (MIM) capacitor is integrated with a high developed area architecture to increase the capacitance density and limit encumbrance. The combination of this architecture with Ta"2O"5 dielectric with a permittivity of 25 allows capacitance densities of more than 15fF/@mm^2. As metal insulator interface is critical, two stacks TiN/Ta"2O"5/TiN and TiN/Ta"2O"5/Cu are integrated among copper interconnects, evaluated and compared.

High permittivity insulators (High-K) are progressively introduced in high-speed integrated passives and devices in order to optimize circuits performances. However, High-K properties are expected to vary with manufacturing process and also frequency as relaxation and resonance mechanisms occur. It is necessary to analyze and evaluate High-K behaviour from DC to microwave frequency. Real permittivity (K or @e'"r) and losses (@e''"r) assessment is required over a wide band of frequency to select the most suitable insulator. The proposed method enables the characterization of as deposited thin (down to 60nm) planar dielectrics integrated below a copper coplanar wave-guide up to 40GHz. Results of Si"3N"4, Ta"2O"5 and STO insulators are presented in this paper.

As device dimensions are scaled down, the variations of electrical and chemical properties within metal electrodes have a critical impact on MOSFETs and Metal/Insulator/Metal (MIM) capacitors characteristics. In this letter, we report on Work Function (WF) measurements performed at deca-nanometer scale using Kelvin probe Force Microscope (KFM). We first demonstrated the relationship between the WF value and the grain crystallographic orientation by combining KFM and Electron Back Scattered Diffraction (EBSD) performed over the same Cu area. Once this relationship was established, KFM was used to provide, in addition to the WF value, the crystallographic properties of PVD TiN films grown on various substrates. Finally we measured an increase of 0.26 eV of the WF of TiN grown by CVD after N"2/H"2 plasma treatment. In the latter case, the modification of the bulk chemical potential by post-treatment has been proposed.

This paper presents the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics. The technology features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 µm2 6T-SRAM bit cell. High Speed (HS) HBT exhibits 320 GHz f T and 370 GHz f MAX associated with a CML ring oscillator gate delay τ D of 2.34 ps. Transmission lines, capacitors, high-Q varactors and inductors dedicated to millimeter-wave applications are also available.

Tantalum oxide (Ta 2 O 5 ) is widely used for MIM (Metal-Insulator-Metal) capacitor owing of its high dielectric constant. This work examines current–voltage and capacitance–voltage characteristics in the 5 K–300 K temperature range. Working at low temperature was chosen in order to freeze trapping mechanisms of the MIM capacitor. The curvature of C – V characteristics radically changes from 5 K to 300 K. The capacitance variation under voltage at 50 K and below can be investigated using the Langevin theory. From this model the permanent dipole moment and the number of dipoles have been extracted. From Poole–Frenkel identification curves, activation energy around 0.20 eV and a dielectric constant of 26 were found for positive polarisation. However, conduction mechanisms cannot be reduced to strick Poole–Frenkel modelling.

International audience

In this study, we have analyzed the influence of different high-k (HK), interfacial layer (IL) and metal gate on the Al effect. We show that hydrogen diffusion during the BEOL process can suppress totally the Al effect on work function. Solutions to stabilize the Al effect with respect to hydrogen diffusion are proposed and a model explaining the hydrogen and Al interaction is provided.

We have used ultra-slow multicharged ions in ultra-high vacuum with a low partial pressure of O2 to grow ultra-thin layers (0.3 to 2.0 nm) of SiO2 on silicon. The advantage of using ultra-slow ions is that they interact with the surface only through their potential energy, not their kinetic energy, so they do not penetrate below the surface, avoiding implanted-induced damages to the substrate. This paper presents several analysis we have performed to qualify these ultra-thin SiO2 layers, such as Fourier transform infrared spectroscopy–attenuated total reflection, Auger electron spectroscopy, X-ray photoelectron spectroscopy, spectroscopic ellipsometry and surface charge analysis. The oxidation process was monitored in situ and in real time using visible light emitted during the irradiation, and the thickness of the SiO2 layers could be controlled. We plan to used these ultra-thin SiO2 layers in next generation MOS gate dielectric stack, as a buffer layer between the channel in silicon and a high-k dielectric.

This letter deals with the electrical and wideband frequency characterizations of metal-insulator-metal capacitors integrating medium-? material, ZrO2. In particular, this letter focuses on the frequency effect on the voltage linearity of these capacitors and material. The dependence of the voltage-capacitance coefficient (VCC) ? is, for the first time, studied from 1 kHz to 1 GHz. Intrinsic or extrinsic material origin of the VCC are discussed.

In this work, a comprehensive investigation of disturb in HfO2-Resistive Random Access Memories (RRAM) integrated in an advanced 65nm technology is presented. The effects of the oxide thickness and RESET conditions on disturb immunity of the High-Resistance-State (HRS) are explored. Constant Voltage Stress is applied on a large amount of samples at various temperatures. Data are collected and analyzed on a statistical basis. The SET dependence to the RESET conditions is investigated and correlated to the length of the induced depleted gap along the conductive filament. The conduction mechanism of the HRS is correlated to the failure/SET process of the RRAM device through a voltage acceleration model. It is shown that thicker dielectric oxide and stronger RESET conditions give rise to longer failure times.

In this study, TiN/La2O3/HfSiON/SiO2/Si gate stacks with thick high-k (HK) and thick pedestal oxide were used. Samples were annealed at different temperatures and times in order to characterize in detail the interaction mechanisms between La and the gate stack layers. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) measurements performed on these samples show a time diffusion saturation of La in the high-k insulator, indicating an La front immobilization due to LaSiO formation at the high-k/interfacial layer. Based on the SIMS data, a technology computer aided design (TCAD) diffusion model including La time diffusion saturation effect was developed.

We have investigated the integration of Hf-based material as Inter Poly Dielectric in flash memories devices. Electrical measurements showed the good properties of SiO2/HfO2/SiO2 stacks. We then interested to the impact of the thermal budget on this specific stack which induces changes in the electrical properties. XPS measurements suggests those changes are due to the presence of an Hf-silicate layer at the SiO2/HfO2 interface.

High-@k dielectrics are promising candidates to increase capacitor integration densities but their properties depend on manufacturing process and frequency because relaxation and resonance mechanisms occur. Complementary characterization protocols are needed to analyze high-@k insulator behaviour from DC to microwave frequencies. The extraction of Plasma Enhanced Atomic Layer Deposition HfO"2 and ZrO"2 complex permittivity was performed up to 5GHz using dedicated test vehicles allowing an in situ characterization as a function of dielectric thickness. The measurement procedure was thus validated, highlighting the potentiality of these two dielectrics to cover a wide range of frequencies.

This work proposes a planar fully depleted “folded” technology integrated on bulk substrate as an innovative solution for upcoming low power nodes to enhance drive current on narrow devices. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide u ltra t hin b ody and b uried oxide (UTB 2 ) devices with improved drive current I on for a given designed footprint W design when scaling the device width . We compare the fabrication and electrical behavior between 〈1 1 0〉 channel, i.e. 0°-rotated wafer, and 〈1 0 0〉 channel, i.e. 45°-rotated wafer, for the same (1 0 0) surface orientation.

This work highlights the new bulk+ technology using high-K dielectric, single metal gate and fully depleted SON (silicon on nothing) channel for sub-45 nm low cost applications. Thin silicon channel (down to Tsi= 8 nm) and thin BOX (Tbox = 15 to 25 nm) are obtained using the SON process (Jurczak, 1999). Transistor performance (Wdesign/Lgate= 90 nm/40 nm) at Vdd = 1.1 V and Ioff < 2 nA/ mum is as high as 1298 muA/ mum for nMOS and 663 muA/ mum for pMOS. In addition, reliability, noise and 6T-SRAM bit cells down to 0.249 mum2 are characterized. Significant improvements with respect to conventional bulk technology are demonstrated.

This work proposes a Bulk+ planar fully depleted ldquofoldedrdquo technology as an innovative cost worthy solution for upcoming low power nodes. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide thin film/thin BOX devices with improved transistor gain beta for a given designed footprint Wdesign. We compare the fabrication between channel, i.e. non-rotated wafer, and channel, i.e. 45deg-rotated wafer, for the same (100) surface orientation.

Atomic layer deposition (ALD) recently emerged as an enabling technology for microelectronic device fabrication. This technique provides the unique capability to deposit ultra thin films with the thickness control, uniformity, step coverage, and electrical/mechanical properties required to support device manufacturing at the 45 nm node and beyond. This paper will review the fundamentals of ALD processing and describe the equipment used. Applications of ALD in the fabrication of advanced gate stacks, on-chip capacitors, and thin film magnetic heads are presented.

A new simple 3D Damascene architecture requiring only one additional mask is introduced for high-density MIM capacitors. TiN/Ta2O5/TiN stack deposited by PEALD has been integrated between Cu interconnect levels to maximize quality factor Q, reaching up to 17 fF/μm2 capacitance. High-performance, breakdown voltages over 15 V and good linearity, C1 = 76 ppm/V and C2 = 63 ppm/V2 at 100 kHz, make this capacitor an unique solution for analog and RF applications embedded in Cu BEOL.

New applications in microelectronics need the integration of high capacitance devices. One way of this development is the integration of capacitors with 3D architecture such as trench fields. The challenge is then to deposit the dielectric material in a highly conformal way within trenches showing high aspects ratios. We have studied and modeled the conformality and the loading effect of Ta 2 O 5 deposited by MOCVD in an analytical way.

High permittivity insulators (high-k) are progressively introduced in high-speed integrated passives and devices in order to optimize circuit performances. However, high-k properties are expected to vary with frequency as relaxation and resonance mechanisms occur. It is necessary to analyze and evaluate high-k behaviour from DC to microwave frequency. Real permittivity (K or epsiv'r) and losses (eepsiv"r) extraction is required over a wide band of frequency to select the most suitable insulator. The proposed method enables the characterization of as deposited thin (down to 60 nm) planar dielectrics integrated below a copper coplanar wave-guide up to 40 GHz. Results of Ta2O5 and STO insulators are presented in this paper

In this letter, we report on Work Function (WF) measurements performed at deca-nanometer scale on various metals using Kelvin probe Force Microscope (KFM). We first demonstrated the relationship between the WF value and the grain crystallographic orientation by combining KFM and Electron Back Scattered Diffraction (EBSD) performed over the same Cu area. Once this relationship was established, KFM was used to provide, in addition to WF value, crystallographic properties of TiN PVD films grown on various substrates. Finally we characterized the effect of N2/H2 plasma treatment on the WF of TiN grown by CVD. In the latter case, the modification of the bulk chemical potential by post-treatment was proposed.

In the late 2000s’ the 32nm Coupled Metal Oxide Semiconductor technology node required the use of a high-k dielectric with a metal gate instead of the historically used silicon dioxide and polysilicon. The aim was to reduce the leakage current between the gate and the channel which became critical for silicon-based gate stacks [1]. However using a high-k metal-gate architecture makes the control of the electrical properties of the transistor really challenging. Indeed the high-k material strongly interacts with its environment during the manufacturing process, which thoroughly changes the device properties. Parameters such as the threshold voltage or the Equivalent Oxide Thickness are not only related to a material selection, but are also subject to modification due to the oxygen diffusion throughout the stack [1]. It has been shown that the oxygen diffusion leads to film thickness modifications, which have a direct impact on these properties [2]. The understanding of the oxygen diffusion dynamics hence becomes mandatory. Our work has been performed inside a cuttingedge STMicroelectronics cleanroom. It focuses on the annealing effects with regard to the oxygen diffusion throughout the stack TiN/HfO2/SiO2/Si. For that purpose, a blank 300mm Si (100) wafer undergoes an oxidizing wet treatment (HF-SC1) to form an 8A-thick chemical oxide layer on its surface. 2nm of HfO2 are deposited onto this wafer by MOCVD with an Applied Material Centura (precursors TDEAH, O2). The annealing processes are made at low pressure (5 torr), with a N2 saturated atmosphere containing 1ppm of O2, at 450°C, 600°C, 750°C and 900°C for 60 seconds. The experiment is renewed with 2nm of TiN deposited on the top of the stack by RF-PVD with an Applied Material Endura tool at low temperature (< 50°C), in order to avoid any thermally activated parasitic reactions. All the samples are characterized with a ReVera VeraFlex II XPS tool as fast as possible after the annealing process. The results show that the annealing without the TiN metal has no noticeable effect with regard to oxygen diffusion, especially at the HfO2 – substrate interface. However as soon as TiN is deposited, the Si2p spectra show an increase of the characteristic signature of SiO2 after annealing at any temperature as shown on figure 1. Fig. 1 XPS spectroscopy of a) HfO2 (20A)/SiO2 (8A)/Si and b) TiN/HfO2 (20A)/SiO2 (8A)/Si (20A), stack after heat treatment in N2 for 60 seconds at various temperatures. Focus on the Si2p region

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Titanium nitride (TiN) films were deposited using plasma-enhanced atomic layer deposition (PEALD) from the organometallic precursor tetrakis-dimethyl-amino-titanium (TDMAT) with hydrogen (H 2 ) as a coreactant. Low-resistivity values lying from 210 to 275 μΩ cm were achieved for 10 nm thick films deposited at low temperature: 150°C. The effects of temperature, plasma time, and plasma power were investigated. It was demonstrated that the chemical reaction is complementary and self-limiting. A minimum energy is necessary to reach the low-resistivity plateau. Chemical and physical properties of the films are also reported and a surface reaction mechanism is proposed. It is suggested that after TDMAT chemisorption to the surface, amines are removed by hydrogen radicals, and at the same time, titanium carbide bonds (Ti-C) are formed. The low resistivity results from the presence of Ti 2 C or Ti 2 N phases in the PEALD TiN film. The industrial viability of this process was also evaluated on 300 mm wafers. Good performances were obtained on wafer-to-wafer uniformity and step coverage, while some improvements related to the within-wafer uniformity are required.

In thin polycrystalline copper film, a direct correlation between the grain crystallographic orientation and the work function has been evidenced by comparing Kelvin probe force microscope (KFM) mapping and electron backscattered diffraction analysis performed over the same region. As a result, work function mapping provided by KFM technique can be used to assess the crystallographic properties of thin layers with a spatial resolution better than 100nm.

The authors report in this letter the effect of interface topography on metal/insulator/metal (MIM) capacitor electrical properties. This analysis was carried out by numerical simulations of the electric field established in a MIM structure with a 45nm thick Ta2O5 film. The metal/insulator interface profiles have been extracted from transmission electron microscopy micrographs of a fully integrated device. This in situ approach allows direct comparison between electrical properties and numerical simulations performed on the same device. Results show that the bottom electrode’s surface roughness induces a large electric field increase at the interface which could explain MIM capacitor’s asymmetrical electrical behavior.