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The model-based library (MBL) matching technique was applied to measurements of photoresist patterns exposed with a leading-edge ArF immersion lithography tool. This technique estimates the dimensions and shape of a target pattern by comparing a measured SEM image profile to a library of simulated line scans. In this study, a double trapezoid model was introduced into MBL library, which was suitable for precise approximation of a photoresist profile. To evaluate variously-shaped patterns, focus-exposure matrix wafers were exposed under three-illuminations. The geometric parameters such as bottom critical dimension (CD), top and bottom sidewall angles were estimated by MBL matching. Lithography simulation results were employed as a reference data in this evaluation. As a result, the trends of the estimated sidewall angles are consistent with the litho-simulation results. MBL bottom CD and threshold method 50% CD are also in a very good agreement. MBL detected wide-SWA variation in a focus series which were determined as in a process window by CD values. The trend of SWA variation, which is potentiality to undergo CD shift at later-etch step, agreed with litho-simulation results. These results suggest that MBL approach can achieve the efficient measurements for process development and control in advanced lithography.

With semiconductor technology moving to smaller patterns after the 45nm hp node, introduction of high-NA immersion lithography progresses, and with it, the challenge of decreasing process latitude. The decreasing lithography tool focus margin is mentioned as one of the key problems of a high-NA immersion lithography process. Tool focus fluctuation has an impact on resist pattern shape and not only does CD change, pattern height also decreases. As a result of previous studies [1][2], it is understood that the resist loss influences pattern formation after etch, and it was confirmed that resist loss is important for CD control. We observe correlation between the resist top roughness and the resist loss, and evaluate the resist loss measurement function by quantifying the resist top roughness. This principle of resist loss detection by measuring roughness is that a changing roughness of resist pattern top is detected as a fluctuation in image brightness on the CD-SEM. A measurement idea was proposed and performance evaluation has already been performed by using one kind of sample. In this study, we demonstrate the validity of resist loss detection by investigating various wafer conditions which contain the dependency by looking at two types of resist and different exposure tool illumination settings. Furthermore, we have confirmed the sensitivity limit of resist loss detection which is approximately above 10nm. Finally, we have discussed improving the resist loss detection sensitivity and considered the applicability of resist loss detection for the litho process monitor.

As dimensions of semiconductor devices shrink further into the nanometer range, transistor performance is improved not only by scaling and adopting boosting technology, but also by adopting new channel material and structure. It is also required to reduce power consumption for mobile devices. In MOS logic devices, 3D-trasistor (FinFET) was adopted to improve switching property. When fabricating, more accurate and higher aspect ratio patterning is required, e.g. fin width reaches 3.7 nm at the 5nm node, where nanowire FET and Ge/III-V channel materials are other candidates [1]. Thus, required accuracy will reach atomic level in the etching process. To realize nm scale etching, new etching process functions are necessary to suppress wiggling, roughening, and degradation of etched layer. At the same time, reasonable productivity is required for mass production. To improve etched profiles, we have been investigated and improved microwave ECR plasma etch tool, e.g. installation of time modulation (pulsing of RF bias, discharge, and gas) technologies, accurate power control of wafer RF bias, end-point monitor, and so on. TM bias (wafer RF bias pulsing) technology is already used in semiconductor fabrication [2]. Lower RF bias power and zero bias condition were effective for extremely high-selective etching. Microwave ECR plasma tool seems to have good affinity to pulsing discharge because it was designed to avoid the drift of plasma density. By using the pulsing discharge, wiggling was suppressed dramatically in DSA mask etching [3]. Gas pulsing technology was also investigated for fin etching. Etching progress and sidewall protection steps were changed cyclically without interruption of the discharge. It was found that etched profile (vertical, etch front flatness, and mask selectivity) was improved [4]. Atomic level precision etching is required in future MOS device fabrication where etched material, etch stop layer, and structure become more complicated. It will be necessary to control lower ion incident energy with vertical direction, lower the gas dissociation to reduce aggressive radical generation and reduce sidewall deposition. We believe multi-pulsing technology (discharge, bias, and gas) and low bias power control at low pressure operation are key technologies to realize atomic level precision etching. [1] ITRS 2013. [2] T.Ono el al, JJAP. 38, 5292 (1999). [3] M. Morimoto et al., SPIE 2014 [9054-18]. [4] M. Tanaka et al., JSAP Autumn meeting, 19p-S10-7, 2014.

The effect of Push–Pull bias (phase-controlled bias) on the plasma potential and sputtering at the chamber-wall was investigated. It was found that the plasma potential could be controlled unrelated to the geometrical configuration of the chamber by using phase-controlled bias. The reason is that by using phase-controlled bias in the plasma with a magnetic field, the earth function of both electrodes facing each other can be controlled. Specifically, with the phase difference set to 180 degrees, the plasma potential was minimized and the decreased energy of incident ions to the chamber-wall reduced sputtering at the chamber-wall. Therefore, a stable process performance without particles caused by a sputtering at the chamber-wall, was expected by using Push-Pull bias in the dielectric UHF-ECR etching system.