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International audience; For display applications, high current and large on/off current ratio are pursued for driving and switching transistors. In this article, a thin film transistor (TFT) device incorporating a buried electrode is proposed, which enables increasing the driving current by reducing the channel length, with the channel length only at the drain side. This lateral short-channel TFT enables increasing the on-current while maintaining the field effect mobility, in comparison to our experimental short-channel vertical TFT structure. Another advantage of the proposed structure lies in the suppression of the Schottky barrier at the source and drain contacts when using high-work-function source/drain contacts for an N-type TFT, with an increased on/off current ratio reaching approximately 106. The suppression of Schottky barrier at the source/drain has been verified by the contact resistance measurements. Even though high driving current is obtained, the off-current is still high due to the weakened electric field at the source/drain sides and needs to be further optimized.

International audience; An organic ambipolar charge trapping non-volatile memory device is proposed based on tris(8-hydroxy quinoline) aluminum(Alq3)/ fullerene(C60)/pentacene double heterojunctions. The double heterojunctions were analyzed and compared with the sole heterojunction. Even though the Alq3/pentacene sole heterojunction shows a negative threshold voltage shift for programming under negative biasing, light illumination is required to efficiently erase. In contrast, for C60/pentacene sole heterojunction, the negative shift of threshold voltage is observed even with a positive erasing voltage. By combining the two trapping layers, a large memory window with fully-electrical programming and erasing is obtained. The efficient programming and erasing of the double heterojunctions structure are analyzed, sufficient electrons can be injected that enables the electrical erasing, and the negative shift of the threshold voltage under positive erasing voltage for the C60/pentacene structure is suppressed due to the suppression of the large built-in potential for the sole heterojunction, which can be verified by a large positive shift for the pentacene/C60/pentacene double heterojunctions.

International audience; The polycrystalline silicon vertical thin-film transistors (TFTs) with different active layer thicknesses of 150 and 300 nm were fabricated by a five-mask process and electrically characterized. The vertical TFT with 150-nm active layer thickness shows comprehensive advantages over its counterpartwith 300-nm active layer, especiallywith a higher ON/OFF current ratio I-ON/I-OFF of more than 10(6) and higher field-effectmobility, excluding the access resistance effect. The electrical parameters were analyzed by the density of states (DOS) calculation, and smallerDOS is deduced for the device with 150-nm active layer for the same energy level. The detailed elucidation of the DOS was analyzed by introducing the intrinsic mobility and the grain boundary barrier height at the flat-band state, which gives the detailed expressions for the DOS. Polycrystalline silicon lateral TFT was also introduced to verify this evaluationmethod.

P and N type polycrystalline silicon has been applied in thin film transistors (TFTs) for driving a range of displays, and for building up complementary metal oxide semiconductor (CMOS)-like circuits. In one aspect, the high driving current is required, which is usually achieved by improving field effect mobility of the active layer. For another, balanced electrical characteristics are required for achieving CMOS-like logic circuits. In this article, in order to increase driving current, P and N type polycrystalline silicon vertical TFTs configuration is proposed that can get rid of the strict requirement of the field effect mobility in order to increase the driving current. In addition, the balanced electrical properties are demonstrated for P and N type vertical TFTs, which are elucidated by the density of states calculations. The simple Simulation Program with Integrated Circuit Emphasis (SPICE) modelling indicates the potential application in CMOS inverter based on our vertical TFTs.

International audience; Thin film transistors (TFTs) with lateral channels are limited in current density due to the design rule. For many applications with improved integration, the introduction of vertical channels reduces channel lengths while increasing current density per unit surface area. In previous works, vertical TFTs have been designed and manufactured using low-temperature polycrystalline silicon technology (T ≤ 600 °C), with a solid phase crystallization (SPC) based process. In this case, the introduction of an insulating layer between source and drain films has resulted in a significant improvement in the electrical characteristics, mainly in the On/Off state current (Ion/Ioff) ratio. However, the active layer is deposited on the sidewalls obtained by plasma etching, and the etching process results in morphological defects on the sidewalls that adversely affect the electrical characteristics. The purpose of this paper is to understand the origin and effects of these defects using different models. Thus, the transfer characteristics are analyzed in detail, with Suzuki method to calculate the density of states, while subthreshold slope method and Grünewald method are adopted to verify the Suzuki method for the deep and shallow trap densities, respectively. These methods provide an approach for DOS calculation independent of temperature-related measurement.