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Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

The electromigration (EM) activation energy ( $\text {E}_{\text {A}}$ ) of alternative metals, such as Ru and Co, was obtained using low-frequency noise (LFN) measurements. High activation energies were expected, but values of ≈1 eV are found, most likely related to diffusion along with the metal-dielectric interface. Wafer-level accelerated EM tests were carried out to compare the LFN $\text {E}_{\text {A}}$ to the EM $\text {E}_{\text {A}}$ in the Ru wires. The calculation of the EM $\text {E}_{\text {A}}$ is found to be strongly dependent on the assumed temperature profile in the wire due to Joule heating (JH). The temperature profile was calculated analytically, assuming the contacts are at ambient temperature. For a void forming in direct proximity of the contact, the EM $\text {E}_{\text {A}}$ then matches the LFN $\text {E}_{\text {A}}$ . For a void at average wire temperature (ambient + JH), $\text {E}_{\text {A}}\approx $ 2 eV. In addition to demonstrating the application of LFN to study EM in alternative metals, this article also cautions for the impact of JH on the calculation of $\text {E}_{\text {A}}$ in interconnects.

The dimensional scaling of the back-end of line (BeOL)interconnects is a significant challenge for the deposition and fill of conductive metals in narrow lines and small vias that are needed to connect the semiconductor devices. Especially at the lower and the smaller interconnect levels, the scaling of the copper (Cu) dual damascene is becoming the limiting factor due to the increase in the resistance-capacitance delay. The increase in RC delay results in a degradation of the chip performance. So, while the scaling in the logic device landscape leads to a continuous improvement of the device performance and an increased transistor density, the Cu wiring in the interconnects systems tend to perform worse when scaling down the dimensions. This paper addresses methodologies to continue the scaling of the BEOL interconnects down to small CD’s like 12nm. For this, process and materials innovation are the key to reduce the interconnect area and its resistance.[1] Examples that will be discussed include Cu hybrid metallization and the use of new conductor materials or integration methodologies like metal patterning. In being the workhorse for building multilevel interconnects, the first desired direction is to push and extend the conventional Cu dual damascene metallization to small dimensions. However, extending Cu is not only challenging from a metal fill point of view, but also from the resistance as well as reliability point of view. The ideal metal that could replace the conventional Cu should have a low electrical resistance in scaled dimensions, have a good thermal conductivity, is resistant against oxidation and possesses a high melting point.[2] This melting is a good measure for the ease of electromigration due to metal diffusion where a high melting point would allow for a reliable operation without the need for a barrier material to prevent it to diffuse. This brings Ru, Mo and W in the picture as interesting material to replace Cu in the vias, and potential later in the lines as well. Figure 1 (left) shows the tabulated via and line resistance predictions for Cu and alternative metals to Cu like Co, Ru, Mo and W (method described elsewhere [3]). The red color coding is used to indicate too high resistance values, where green indicates the desired target resistance. The resistance benefit for the use of Ru, Mo or W compared to Cu is clearly visible in the table. An efficient way to introduce a new alternative metal in the Cu interconnect metallization without being too disruptive is using a selective metal deposition for the vias landing on the exposed bottom metal (Fig.1 middle). After the vias are filled using a selective metal-on-metal deposition with a barrierless metal like Ru or W [4,5], the remainder of the structures can be filled using the conventional Cu metallization scheme. This process is called a Cu hybrid metallization scheme. Filling the vias before the Cu line metallization, improves the process window and yield for the Cu gapfill. Challenges for the selective deposition of metals in vias will be discussed. The XTEM in Figure 1 (right) shows a successful example of the metal prefill in a via hole with bottom CD of 14nm. The via is nicely filled with the metal while the top lines in the dielectric that are not connected to vias do not show any non-selective deposition. Even though the vias are becoming more and more critical in the signal routing on a system-on-chip level, the resistance penalty for the Cu lines is unacceptable at small CDs as can be seen in the table in Fig.1. But eventually, the Cu electromigration will set the limit because at 10nm CD copper lines are not expected to meet electromigration requirements anymore [6]. This is then an inflection point to also replace the lines with alternative metals like Ru, Mo or more exotic conductors like binary metals. For these metals, the challenges in the line fill, processing, and integration will be discussed which may lead to the introduction of the so-called semi-damascene module [7] instead of using the dual damascene methodology. [1] J. Clarke et al, IEEE VLSI 2014, p. 176 [2] D. Gall et al, J. Appl. Phys. 2016, 119, p.085101 [3] I. Ciofi et al, IEEE transactions on Electron Devices 2017, 64 (5), p.2306 [5] M.H. van der Veen et al, Proc. of the IITC 2021, S7-2 [4] M. van der Veen et al, Proc. of the IITC 2020, p.16 [6] K. Croes et al, IEDM 2018, p 5.3.1 [7] Zs. Tőkei et al, IEDM 2020, p 32.2.2 Figure 1

In this paper, we present a modeling study to investigate the self-heating effect on advanced metallization schemes with airgaps using an experimentally calibrated finite element model. We compared N3 technology node with N2 integrated with airgaps. Despite the higher metal density of the fully dense Ru lines (50%) at the lower metal levels in the N2 structure with airgaps, the N2 stack is more susceptible to self-heating than the N3 structure with 25% line density, showing that the IMD has an important impact on the interconnect self-heating. We quantified the effect of the line density and IMD on the interconnect temperature increase. We found that decreasing the line density from 50% to 15% increases the temperature with 40% in the interconnect structure. A reduction of the low-k thermal conductivity values below 1 W/m-K shows to accelerate the temperature increase in the BEOL.

In this paper the electromigration (EM) limits of Cu nano-interconnects are studied considering the impact of microstructure in Co cap schemes and performance booster technologies i.e. via pre-fill and scaled barrier-liner schemes. A combination of experimental and physics-based modelling approaches is employed to provide fundamental understanding of the involved mechanisms. The results show that linewidth reduction, higher trench depth, i.e. larger aspect ratio (AR) and thinner barrier and liners result in more polycrystalline copper texture. It was found that at 10.5 nm linewidth, ~95% of the nano-interconnect length is polycrystalline while for 25 nm linewidth this is ~85%. A 90% drop of jfail i.e. the current density that induces failure at 10 years, was found by scaling linewidth from 25 nm to 10.5 nm in Cu interconnects with Co cap. Experiments show a 70% drop of time to failure due to barrier film thickness scaling from 3 nm to 2 nm for PVD TaN. Utilization of Co cap and via prefill were found to increase jfail by ~10 fold and ~3 fold, respectively.

In this paper we present a semidamascene integration approach for interconnect devices as an alternative to dual damascene. A Ru layer is deposited to fill vias and provide an overburden in which we will form lines using subtractive metal etching, enabling easy access to higher line aspect ratios without the need for metal CMP. Subsequent dielectric deposition forms airgaps between the lines. Devices fabricated in imec’s 300mm cleanroom have demonstrated with >80% reproducibility for line structures with 30nm metal pitch. We also present reliability results with extrapolated lifetime > 10 years and benchmark the mechanical strength of semidamascene devices to traditional dual damascene.

Cu pumping is defined as the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread. In previous publications both a lognormal distribution and a distribution of the maximum of two normal variables were used to fit experimental data. In this paper, these two types of statistical distribution are compared, showing that the maximum of two normal distributions provides a better fit, in particular at the right tail which is more significant for the potential reliability impact of Cu pumping. Also, it is shown how Cu pumping is determined by the network of random high angle grain boundaries in the Cu region near the TSV top, as an extension of a previous analysis which occurred at the TSV top surface only. This relation between Cu pumping and Cu microstructure provides a physical interpretation of the maximum of two normal distributions, based on the deformation mechanisms underlying Cu pumping.

This paper demonstrates the deteriorating electromigration (EM) reliability of Cu interconnects when scaling the metal pitch from 54 to 44nm. The study is carried out using a new EM test method based on low-frequency noise. Both EM lifetime and activation energy are found to decrease when scaling the line-width from 32 to 22nm. The decreasing activation energy is attributed to an increased number of grain boundaries and therefore enhanced grain boundary diffusion in narrow lines. The paper also shows that EM lifetimes can be qualitatively predicted based on the data obtained from LFN measurements.

Atomic layer deposition of ruthenium is studied as a barrierless metallization solution for future sub-10 nm interconnect technology nodes. We demonstrate the void-free filling in sub-10 nm wide single damascene lines using an ALD process in combination with 2.5 Å of ALD TiN interface and postdeposition annealing. At such small dimensions, the ruthenium effective resistance depends less on the scaling than that of Cu/barrier systems. Ruthenium effective resistance potentially crosses the Cu curve at 14 and 10 nm according to the semiempirical interconnect resistance model for advanced technology nodes. These extremely scaled ruthenium lines show excellent electromigration behavior. Time-dependent dielectric breakdown measurements reveal negligible ruthenium ion drift into low-κ dielectrics up to 200 °C, demonstrating that ruthenium can be used as a barrierless metallization in interconnects. These results indicate that ruthenium is highly promising as a replacement to Cu as the metallization solution for future technology nodes.

This article identifies four major reliability challenges related to TSV-based 3-D integrated circuits and their solutions that are being developed at imec.

We describe an X-ray diffraction imaging technique for nondestructive, in situ measurement of die warpage in encapsulated chip packages at acquisition speeds approaching real time. The results were validated on a series of samples with known inbuilt convex die warpage, and the measurement of wafer bow was compared with the results obtained by optical profilometry. We use the technique to demonstrate the impact of elevated temperature on a commercially sourced micro quad flat nonlead chip package and show that the strain becomes locked in at a temperature between 94 °C and 120 °C. Using synchrotron radiation at the Diamond Light Source, warpage maps for the entire $2.2~\textrm {mm} \times 2.4~\textrm {mm} \times 150$ - $\mu \text{m}$ Si die were acquired in 50 s, and individual line scans in times as short as 500 ms.

High-aspect-ratio (HAR) Ru power rails, buried in front-end-of-line (FEOL) oxide, can potentially replace conventional middle-end-of-line (MOL) Cu power rails. The HAR feature can boost performance by reducing resistance and voltage drop along the power line. The buried nature, helps to minimize standard cell height by freeing up routing resources at MOL, enabling overall area scaling. This paper demonstrates, Ru lines of aspect ratio up to 7, at a CD of 18 nm. Line resistance at these dimensions, measures at 60 Ω/µm, with the minimum electrical resistivity of 8.8 µΩcm, as extracted from the temperature-controlled-resistance (TCR) measurements. HAR Ru lines are also found to withstand very high FEOL thermal budgets, such as 1000 °C activation anneal for 1.5 s. The combination of all these factors, make HAR Ru buried power rail, a promising scaling booster for next generation technology nodes.

We show the first electromigration (EM) failures of full ruthenium interconnects with a cross sectional area of 60nm2. The void is observed at the anode, which demonstrates that in p-type metals, such as Ru, the electromigration force acts in the direction of the electric field. The conventional representation of electromigration as electrons transferring their momentum onto the metal ions, thus has to be adapted for such metals. Moreover, we find that diffusion at the Ru-SiO 2 interface is the dominant diffusion mechanism for EM failure in these specific Ru lines.

To predict the impact of technological variables such as materials, dimensions, interfaces, and operating conditions on Cu electromigration, in this study a hybrid modeling framework is developed by coupling a global Korhonen-type electromigration modeling module with a cellular automaton-based void dynamics module. The modeling framework is corroborated and benchmarked using experiments on Cu interconnects and is used to predict the impact of scaling on Cu electromigration induced stress evolution. The simulations shed light on the impact of dimensional scaling on stress kinetics, void nucleation, and growth phases, where the nucleation phase is found to become longer than the growth phase and voids are found to grow relatively more rapidly upon nucleation in highly scaled linewidth. In addition, the simulations predict 22% lower median time to failure and a higher variability of time to failure for downstream vs upstream electromigration modes due to the more critical impact of near via voiding in downstream cases. Lending further credence to its predictive merits, the model predicts and explains complex R-shift signatures occurring at high temperature electromigration experiments due to void dynamics.

This paper reports on the mechanical design, the fabrication technology and the key performance and reliability aspects of novel 0-level thin film vacuum packages for (RF-)MEMS. The packages typically feature a dielectric cap composed of nanoporous alumina and PECVD silicon nitride with a total thickness between 6 and 8.3 μm. The surface micromachining fabrication process is based on a relatively simple method for the wafer-level formation of freestanding nanoporous alumina membranes, featuring extremely narrow cylindrical nanopores with diameters in the range of 10–20 nm and aspect ratio exceeding 100. The package impact on an encapsulated coplanar waveguide (CPW) is minimized (up to 67 GHz) by locally narrowing the RF feedthroughs underneath the package anchor. Furthermore, the hermeticity of various package configurations is evaluated by means of optical monitoring of the cap deflection under different environmental conditions, including short-term exposure to helium and long-term (up to 14 months) exposure to air. Finally, a comprehensive investigation of the reliability of the thin film packages and their compatibility with high-pressure epoxy overmolding 1-level packaging is discussed.

We demonstrate 10 nm half-pitch (HP) Ruthenium interconnects filled by atomic layer deposition (ALD). The resistivity and the cross-sectional area of Ruthenium interconnects were determined via the Matthiessen's rule method. We find that the resistivity of Ru was rather independent of the cross-sectional area of the interconnect, increasing from 12 µΩcm for larger lines to 15–17 µΩcm for cross-sectional areas of 200–300 nm2. 10 nm HP Ru lines showed no electromigration failures at 5 MA/cm2 and 300°C during 1000 hours. Time-dependent dielectric breakdown measurements indicated that Ruthenium does not require a diffusion barrier on both dense and porous low-κ dielectrics.

Thermal compression bonding (TCB) process in combination with a pre-applied underfill material has been developed and investigated for assembling 20 μm pitch Sn-based micro bumps. It is found bonding force has a profound impact on the joint formation behavior. A low bonding force produces bump joints with heavier underfill entrapment and incompletely reacted solder. A higher bonding force leads to more solder squeezing-out, leaving a thin and completely reacted inter-metallic compound (IMC) layer in the joints. Electrical measurement of the daisy chains on the as-bonded chips does not reveal any significant difference between the samples made with different bonding forces. The reliability of the two types of joints were further studied in two post-bonding tests, namely the resistance measurement of daisy chains at an elevated temperature and stack-level thermo-cycling test. Both tests show a better reliability performance from the bump joints with less underfill entrapment and completely reacted IMC layer.

In this paper, we report on the design, fabrication, packaging, and testing of very reliable CMOS-integrated 10-cm2 11-megapixel SiGe-based micromirror arrays on top of planarized six-level metal 0.18-?m CMOS wafers. The array, which is to be used as a spatial light modulator (SLM) for optical maskless lithography, consists of 8 ?m × 8 ?m pixels, which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. Due to very stringent requirements on mounted-die flatness (< 0.01 mrad), the first level packaging of SLM die is done using specially designed SiC holders. To avoid trapped particles between the die and holder, which would jeopardize the flatness spec, special backside cleaning of the dies (less than or equal to one 0.8-?m particle/cm2) is needed before mounting the SLM die on the holder. To enable this backside cleaning and to avoid front-side particles during dicing, handling, and wire bonding, a temporary waferor zero-level packaging cap, which can be placed and removed at room temperature, was developed. The dynamic white light interferometer measurements of packaged dies showed that 99.5% of the 123 648 mirrors tested are within the spec. In addition, a stable average cupping of below 7 nm, an rms roughness of below 1 nm, and a stable actuation of over 2.5 teracycles are demonstrated.

This paper discusses optical systems for automatic, wafer or chip level measurements of metrology, functional yield and reliability of MEMS. The functionality of the systems is demonstrated on megapixel arrays of SiGe micro-mirrors. The back-bone of the systems is formed by existing commercial systems, but home-developed procedures and software were written to extend their functionality and applicability.

Cu pumping is the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures during back-end of line (BEOL) processing. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread. As potential BEOL reliability issues due to Cu pumping will first occur at the highest pumping TSVs, they can be mitigated if the fundamental cause for this large intrinsic spread is known and under control. This paper describes a clear correlation between Cu pumping and TSV Cu microstructure based on the grain size at the top of 5×50 μm TSV, disregarding twin boundaries. For the mitigation of TSV Cu pumping the ideal microstructure was shown to consist of a single grain spanning the whole TSV cross section, bringing down the highest measured Cu pumping value from 248 nm to 73 nm. This effect was attributed to the absence of rapid diffusion paths and grain boundary sliding ability.

Irreversible extrusion of Cu from through-silicon vias (TSVs) during high-temperature processing steps presents an important potential back-end-of-line (BEOL) reliability issue. Commonly this reliability risk is mitigated by introducing an anneal after Cu plating for TSV fill. This paper presents the impact of the post-plating anneal temperature and time on residual Cu pumping during a sinter for 20 min at 420 °C, for two different TSV dimensions. Using optical profilometry, in total ~ 4000 TSVs were measured, allowing detailed statistical analysis. Within one sample the Cu pumping values were found to be log normally distributed, implying an intrinsically large spread. Lower residual Cu pumping values were found in TSVs annealed at higher temperatures and for longer times, with the sinter conditions of 20 min at 420 °C confirmed as optimal post-plating anneal conditions. The larger TSVs showed more pumping in the average TSV, but at the tail of the distribution the Cu pumping behavior was the same as for the smaller TSVs. This implies that the impact of Cu pumping on BEOL reliability is identical for both sets of TSV dimensions, suggesting that the impact of Cu pumping on BEOL reliability is not necessarily reduced by reducing TSV dimensions.

After a brief overview of possible failure mechanisms and failure defects that can occur in radio frequency microelectromechanical systems (RF MEMS), this chapter focuses on three specific reliability issues: charging, because it remains the most important problem for capacitive RF MEMS; electrostatic discharge, because it is less known as a possible failure cause for MEMS; and package hermeticity, because this is an often underestimated problem for RF MEMS.

A poly-SiGe technology enabling a dense array of micro-cantilevers and tips on CMOS is demonstrated. Built from a dual-thickness structural layer, the cantilevers feature a very small initial bending and have a compliant torsional suspension with a stiffness of 3×10−10 Nm/rad. Sharp tips are formed in a low-temperature amorphous silicon layer by isotropic plasma etching. An electrical read/write system is formed by connecting the tip to the CMOS with a suspended platinum trace, running on top of the cantilever.

In this paper various non-standard methods and instruments for the functional, yield and reliability analysis of MEMS are discussed. Most of these methods are based on existing instruments, involving electrical, optical or mechanical measurements. We present either alternative applications of existing techniques, new methodology for data extraction, or adaptation/automation of the techniques for automatic chip or wafer level measurements.

In this paper we report for the first time on the fabrication of very reliable CMOS-integrated 10 cm2 11 MPixel SiGe-based micro-mirror arrays on top of 6 level metal CMOS wafers. The array, which is to be used as Spatial Light Modulator (SLM) for optical maskless lithography [1,2,3] consists of 8 mum x 8 mum pixels which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. The pixel density is almost double compared to the state-of-the-art [4]. A stable average cupping below 7 nm, an RMS roughness below 1 nm and long lifetime (>1012 cycles, no creep [5]) are demonstrated.