45 results on '"Oldiges, Phil"'
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2. The Effects of Threshold Voltage and Number of Fins Per Transistor on the TID Response of GF 12LP Technology
3. Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond
4. Examination of Spatial Frequency Dependence of Line Edge Roughness on MOS Device Characteristics
5. Hole Mobility Enhancement Modeling and Scaling Study for High Performance Strained Ge Buried Channel PMOSFETs
6. A Practical Approach to Modeling Strained Silicon NMOS Devices
7. Finite element based three dimensional Schrödinger solver for nano-scale devices
8. Predictive Soft Error Rate Evaluation System
9. Defect and grain boundary scattering in tungsten: A combined theoretical and experimental study.
10. Characterization of parasitic bipolar transistors in 45 bipolar silicon-on-insulator technology
11. Design implications of single event transients in a commercial 45 nm SOI device technology
12. Low-energy proton-induced single-event-upsets in 65 nm node, silicon-on-insulator, latches and memory cells
13. Latch design techniques for mitigating single event upsets in 65 nm SOI device technology
14. Single-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cells
15. Modeling single-event upsets in 65-nm silicon-on-insulator semiconductor devices
16. Chip Power-Frequency Scaling in 10/7nm Node
17. Impact of heater configuration on Reset characteristics of PCM Mushroom cell
18. 2-D MOSFET modeling including surface effects and impact ionization by self-consistent solution of the Boltzmann, Poisson, and Hole-Continuity equations
19. Technique for Asymmetric Source/Drain Resistance Extraction on a Single Gate Length MOSFET
20. First-Principles Investigations of TiGe/Ge Interface and Recipes to Reduce the Contact Resistance
21. Low Energy Proton SEUs in 32-nm SOI SRAMs at Low Vdd
22. Theoretical Determination of the Temporal and Spatial Structure of [Alpha]-Particle Induced Electron--Hole Pair Generation in Silicon
23. Density scaling beyond the FinFET: Architecture considerations for gate-all-around CMOS
24. Toward Ultimate Scaling of MOSFET
25. Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond
26. Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction
27. Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond
28. Finite element based three dimensional Schrödinger solver for nano-scale devices
29. Dielectric isolated FinFETs on bulk substrate
30. Ab initio Study of Metal Grain Orientation-Dependent Work Function and its Impact on FinFET Variability
31. Meeting the Challenge of Multiple Threshold Voltages in Highly Scaled Undoped FinFETs
32. A Comparison of Short-Channel Control in Planar Bulk and Fully Depleted Devices
33. Suppression of boron diffusion in deep submicron devices
34. Characterization of Parasitic Bipolar Transistors in 45 nm Silicon-on-Insulator Technology
35. Non-planar device architecture for 15nm node: FinFET or trigate?
36. Session 36: Modeling and simulation enhanced mobility and III-V devices
37. Multi-bit upsets in 65nm SOI SRAMs
38. Protecting Big Blue from Rogue Subatomic Particles
39. Modeling & Simulation - Performance Analysis And Transport Modeling
40. Simulation Study on Channel Length Scaling of High Performance Partially Depleted Metal Gate and Poly Gate SOI MOSFETs
41. Strained SiGe/Ge Buried Channel pMOSFETs Design For High Performance Applications
42. Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond.
43. A Model for Reverse Short Channel Effect and Capacitance‐Voltage Characteristics
44. FinFET Design Considerations Based on 3-D Simulation and Analytical Modeling.
45. Comparison of α-Particle Induced Charge Collection on MOS Capacitors Using a DC Tester
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