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Several major electron scattering mechanisms in tungsten (W) are evaluated using a combination of first-principles density functional theory, a Non-Equilibrium Green's Function formalism, and thin film Kelvin 4-point sheet resistance measurements. The impact of grain boundary scattering is found to be roughly an order of magnitude larger than the impact of defect scattering. Ab initio simulations predict average grain boundary reflection coefficients for a number of twin grain boundaries to lie in the range r=0.47 to r=0.62, while experimental data can be fit to the empirical Mayadas-Schatzkes model with a comparable but slightly larger value of r=0.69. The experimental and simulation data for grain boundary resistivity as a function of grain size show excellent agreement. These results provide crucial insights for understanding the impact of scaling of W-based contacts between active devices and back-end-of-line interconnects in next-generation semiconductor technology. [ABSTRACT FROM AUTHOR]

This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets. Index Terms--Modeling, radiation event, single event transient (SET), single event upset (SEU), soft error.

Experimental data are presented showing that low energy (< 2 MeV) proton irradiation can upset exploratory 65 nm node, Silicon-On-Insulator circuits. Alpha particle SER data, modeling and simulation results provide a plausible mechanism. This work suggests that track structures need to be understood and effectively modeled, especially for small, modern devices. Index Terms--Alpha particles, direct ionization, protons, radiation effects, simulations, soft error rate.

This paper describes techniques for mitigating single event upsets in master-slave flip-flop latches in 65 nm SOI device technology. Techniques are explained, modeled, and measured with hardware experiments. Index Terms--Alpha particle, modeling, radiation event, single event upset (SEU), soft error.

Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled. Index Terms--Critical charge, Qcrit, SER, single event upsets, SOI.

This paper describes a technique for modeling single-event upsets due to ionizing radiation in a partially depleted silicon-on-insulator (SOI) MOSFET device. Two current pulses are used, one connected between the drain and body of the device, and the other connected between the body and source of the device. The physical representation of these two current sources is described in detail. Circuit modeling is verified against drift-diffusion field solver modeling and hardware experiments. The effects of manufacturing variation and operating condition variation on the qCrit of circuit storage elements are explored. Index Terms--Alpha particle, modeling, radiation event, single-event upset, soft error.

A two-dimensional simulator based on the deterministic self-consistent solution of the Boltzmann, Poisson and Hole-continuity equations effectively models MOSFETs. The direct use of the collision integral is used to study the effect of impact ionization on electron-hole pair formation. It is useful for mainstream device simulation and provides the distribution function from which most device characteristics can be derived. It requires only three equations, unlike the hydrodynamic model and is based on specific scattering mechanism and band-structure.

Physics-based modeling of the impact ionization process in silicon was performed to determine the time constants and radial distribution of electron-hole pairs after an [Alpha]-particle strike. The radial distribution exhibited a Gaussian shape with a radius of approximately 50 nm. The impact ionization process took place over a period of less than approximately 500 fsec, implying time constants for use in semiconductor device simulations on the order of a few hundred fsec, a value much smaller than has been used in earlier device simulation work. Device simulations then show that the implication of using these shorter time constants is the creation of a higher concentration of electron-hole pairs at shorter times that cause stronger shunting effects for [Alpha]-particle strikes between source and drain of MOS transistors.

Investigates design consideration of FinFET by three-dimensional (3-D) simulation and analytical modeling. Short-channel effects by 3-D distributive simulation; Short-channel effects by 3-D analytical modeling; Insights into device design; Conclusion.