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Gallium oxide (G a 2 O 3 ) is a promising ultra-wide bandgap material offering a large bandgap (> --> 4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga 2 O 3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga 2 O 3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga 2 O 3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga 2 O 3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga 2 O 3 power transistors. [ABSTRACT FROM AUTHOR]

As the electromagnetic environment becomes increasingly complex and power density continues to increase, the reliability and safe operation of gallium nitride (GaN) high electron mobility transistors (HEMTs), which are widely used in the field of high-power radio frequency amplifiers, are severely jeopardized. In this study, the effects and mechanism of high-power microwave on AlGaN/GaN HEMT power amplifiers were explored. A novel effect phenomenon, which is entirely distinct from the reported high-power microwave damage mechanism of GaN devices, was uncovered. This phenomenon exhibits extremely strong field effect characteristics. Through further effect experiments and numerical simulations, it was affirmed that the failure mechanism is as follows: high-power microwave couples to the drain electrode, creating a high electric field, leading to avalanche breakdown near the gate and below the drain electrodes, forming a leakage channel. Subsequently, under the action of the device's bias voltage, extensive burning of the device occurs, which is a stimulating burnout effect. [ABSTRACT FROM AUTHOR]

Density functional theory was utilized to assess the influence of In alloying on the spontaneous (Psp) and piezoelectric (Ppe) polarization of ε-Ga2O3 heterostructures with In concentrations ranging from 0% to 50%. The analysis demonstrated a decrease in both Psp and Ppe with an increase in In concentration, described by the equations Psp = −9.5947x + 24.81 and Ppe = −0.6217x (where x represents the In concentration, with units in μC/cm2). Additionally, the polarization-induced two-dimensional electron gas (2DEG) density within ε-InGaO/ε-Ga2O3 heterostructures was examined using a one-dimensional Schrödinger–Poisson solver. An inverse correlation was observed between 2DEG density and epitaxial thickness across all undoped In-alloyed samples. Furthermore, achieving high 2DEG densities (exceeding 1013 cm−2) is significantly facilitated by n-type doping concentrations above 1017 cm−3 in ε-InGaO. These insights not only augment the understanding of polarization effects in ε-Ga2O3 heterostructures but also provide a strategic framework for enhancing 2DEG density in ε-Ga2O3-based devices, which offers significant potential for advancing ε-Ga2O3-based high electron mobility transistors for power and RF applications. [ABSTRACT FROM AUTHOR]

Battery storage systems are becoming very popular around the world. However, they are mainly used in industry for high-performance applications. Domestic use is still sporadic due to size and cost issues. This work overviews basic conceptual designs for a cost-effective battery storage system. The main specificity of the proposed systems is the use of commonly available recycled batteries from household appliances such as laptops and backup power supplies. The circuit topology considered is a 3S (three cells in series) configuration. This is because such wiring arrangements are those that are most often found in the home appliances described here. The technical solutions of the device itself focus on the ratio of the efficiency of the whole system to the production cost. Given the above, attention was paid to the simulation analysis of the operating modes, which directly influenced the components' price. Changing the switching control scheme of the power transistors makes it possible to reduce the requirements for the driving components used with minimal impact on the power conversion efficiency (Δη 1–4%). According to the established findings, a prototype was made on which the simulation findings were verified; then, we further focused on the experimental measurement of the efficiency of the MPPT converter and conducted an analysis of a methodology in which we measure the deviation from the actual point of maximum power. The simple possibility of parallelizing the individual storage devices will again help improve the system's overall efficiency. This makes the system suitable for use in small spaces such as houses, garages, cellars, etc. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) power devices are becoming central components in high voltage electronics. However, defects at interfaces and in the bulk continue to severely impact their reliability and performance. Here, we develop a charge pumping method to characterize SiC/SiO 2 interface defects in fully fabricated commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The method is then used to address spin states at the SiC/SiO 2 interface via charge pumping electrically detected magnetic resonance (CP-EDMR). We apply these methods to investigate the power MOSFET after electron irradiation over a dose range of 10 13 − 10 17 cm − 2 . We finally discuss CP-EDMR as a technique to interrogate spins during device operation for real-time monitoring of the device quality, performance, and degradation and as a probe for local magnetic fields. [ABSTRACT FROM AUTHOR]

CMOS analog amplifier circuits are integral components in the signal‐processing stages of consumer electronics. They also find applications in advanced imaging systems, augmented reality devices, smartphone audio applications, power management circuits, etc. The differential and two‐stage operational amplifier circuits must be optimally designed for next‐generation consumer electronics devices, where speed and sizing are important constraints. This nonlinear constrained optimization problem can be resolved using evolutionary optimization techniques. This article proposes an efficient design technique for a CMOS differential amplifier circuit and CMOS two‐stage op‐amplifier. A well‐known optimization problem is the particle swarm optimization (PSO). PSO is a robust optimization method but may suffer from premature convergence and slow convergence speed. The evolutionary technique used here is the modified version of the PSO, named Levy flight, power function, and Singer map utilized PSO (LPSPSO). In PSO, the Levy flight can enhance the exploration capability and improve the convergence speed. The proposed evolutionary technique reduces the individual circuits' area and design time while satisfying the design constraint. The LPSPSO‐based results are authenticated with SPICE. SPICE results demonstrate that LPSPSO is an efficient evolutionary technique than formerly reported methods in designing analog amplifiers in terms of MOS area, gain, power dissipation, etc. [ABSTRACT FROM AUTHOR]

Machines with highly saturated magnetic circuits are utilized to maximize drive efficiency. However, their control is non-trivial due to highly non-linear characteristics, and therefore, an accurate parameter identification procedure is crucial. This paper presents and validates a comprehensive flux linkage identification procedure. Several steps needed for accurate parameter identification and their influence on the estimation results are described. The impact of all main parts of the electrical drive, i.e., dead times introduced between switching off and switching on the power transistors, phase delay from the current low-pass filters, delay from the control system, and misalignment of the d – axis angle due to the machine asymmetries is considered and partially eliminated. An improved identification procedure with the look-up table-based dead time compensation and estimation of equivalent circuit resistance is applied to estimate the parameters of the highly saturated PMSM traction machine from the fourth generation of the Toyota Prius, and the obtained results are compared with a Finite Element Method-based model of this machine. Finally, dynamic test results are conducted to prove the proposed approach's accuracy. [ABSTRACT FROM AUTHOR]

The three-level neutral-point clamped inverter represents a significant advancement in direct torque-control systems for asynchronous motors. A significant achievement of this study lies in the comprehensive analysis of a random frequency-modulation algorithm, which demonstrates its efficacy in substantially reducing the amplitude of harmonic oscillations and minimizing switching losses. This simplifies filter design and minimizes thermal dissipation in power transistors, thereby enhancing the overall reliability and efficiency of the system. Additionally, the implementation of a six-position torque regulator with a fixed sensitivity zone, applied in direct torque control based on the three-level inverter, improves the stability of the stator flux linkage and reduces the switching frequency of transistors. Numerical simulations conducted in the Matlab/Simulink environment indicate that the proposed algorithm reduces switching losses by 15% during transient states and by 2% during steady-state operation while increasing the system's efficiency by 2% compared to conventional methods. These findings highlight the potential of the proposed solutions for application in energy-efficient drive systems. [ABSTRACT FROM AUTHOR]

Real biological neurons are dynamical systems that can process a nonlinear, arbitrary input signal with a dynamic threshold voltage, exhibit refractory time, and have a smooth F – I curve. This paper presents a generalized bio-plausible neuron model with refractoriness, frequency adaptation, and dynamic threshold. The spiking characteristics of the generalized neuron are enhanced with less circuitry and fewer parameters compared to older circuits. The proposed silicon neuron can generate all known spiking behaviors, just like a biological neuron. The circuit is designed using a 180 nm standard CMOS process. The entire design uses 22 transistors with a total power consumption of only 2 nW for a 1 nA step current at a spike frequency of 122 Hz. The power consumption and spike frequency rate depend on the input current. The proposed neuron is also capable of displaying both Type I and Type II frequency response characteristics. In addition, our neuron model underwent Monte Carlo simulation with 1000 sample runs to assess its robustness and stability against process variations and uncertainties. The results indicate that the average energy consumption of the proposed neuron model falls within the range of 16 pJ to 68 pJ. [ABSTRACT FROM AUTHOR]

In wireless sensor networks, conserving power is vital for prolonging battery life. This research introduces a groundbreaking solution: a 9T carbon nanotube‐field effect transistor (CNTFET) based SRAM cell (9T SRAM) designed to optimize power consumption and stability. Through meticulous analysis, the performance of this 9T SRAM cell is quantified. Power consumption metrics reveal impressive figures: the write, hold, read, and dynamic power are measured at 0.21 nW, 0.32 nW, 15.28 μW, and 8.09 μW, respectively. Furthermore, the Write SNM (WSNM), Hold SNM (HSNM), and Read SNM (RSNM) are found to be 380.11, 390.22, and 390.31 mV, respectively, indicating robust stability. The proposed bit cell has a write and read delay of 95.1 and 39.6 pS, respectively. Incorporating stacked transistors diminishes power consumption, while the decoupled read technique boosts the stability of the proposed bit cell. By comparing these results with existing SRAM cells, the superiority of the proposed 9T SRAM cell in terms of power efficiency becomes evident. Notably, it outperforms earlier models, making it an ideal candidate for integration into wireless sensor networks. These findings are supported by simulations conducted using HSPICE, alongside a 32 nm CNTFET model sourced from Stanford University. [ABSTRACT FROM AUTHOR]

Copyright of Técnica Industrial: Revista Cuatrimestral de Ingeniería, Industria e Innovación is the property of Fundacion Tecnica Industrial and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this study, we present the design, simulation, and implementation of a DC-DC synchronous buck converter utilizing IISB's 2 μ m 4H-silicon carbide (SiC) complementary metal–oxide–semiconductor (CMOS) technology. The converter is designed to meet the demands of modern integrated circuits, particularly in the field of integrated power management. The SiC technology offers enhanced performance and reliability at high temperatures, making it especially suitable for applications that operate in these conditions, including automotive systems, and aerospace, among others. The power transistors and gate drivers are fully integrated on-chip, optimizing efficiency and minimizing footprint. Additionally, the study contributes to the understanding of SiC technology and its application in integrated circuit design. Simulation results demonstrate a peak efficiency of 86.6% at 120 mA load current and 84.8% at 300 mA load current, showing the converter performance under different operating conditions. Furthermore, at high temperatures (295 °C), the converter achieves an efficiency of 89.6%, demonstrating its robustness and versatility in extreme environments. These findings contribute to the advancement of integrated circuit design and facilitate advancements in more efficient and robust power management solutions. [ABSTRACT FROM AUTHOR]

In this Letter, we present a p-GaN gate enhancement-mode GaN-on-Si high-electron mobility transistor fabricated using Mg-acceptor re-passivation realized through ammonia plasma treatment. The gate-to-source and gate-to-drain access regions of the device were treated with ammonia plasma using a plasma-enhanced chemical vapor deposition system, resulting in the formation of a high-resistivity GaN cap layer. The fabricated device has a high threshold voltage (VTH) of 2.0 V and a low gate reverse leakage current (IGR) of 10−11 A/mm. A breakdown voltage (BVOFF) of 670 V together with a specific on-resistance (Ron,sp) of 0.87 mΩ cm2 was obtained in a device with LGD = 6 μm. The measured dynamic on-resistance (Ron,d) at a quiescent drain voltage (Vds,q) of 600 V with a stress time of 10 and 120 s is 1.06 and 1.34 times of the static on-resistance (Ron,s), respectively. Good thermal stability of VTH and gate current IG were observed after a thermal stress at 175 °C for 100 h. The developed fabrication techniques exhibit a great potential to be applied into GaN power transistors. [ABSTRACT FROM AUTHOR]

In this work, the effect of offset channel length (Loffset) and the dielectric layer thickness (d) on the InSnO/InGaZnO (ITO/IGZO) dual-active-layer (DAL) high-voltage thin-film transistors (HV-TFTs) is systematically investigated. The characteristics of the DAL HV-TFTs resemble that of GaN high electron mobility transistors, wherein the breakdown voltages (VBD) reach saturation at a certain Loffset, and the on-resistance (Ron) linearly increases with Loffset. The linear fitting of Ron vs Loffset indicates that d has a multifaceted impact on the performance of HV-TFTs. In addition to its theoretical role in transistor models, d also influences the channel doping concentration and sidewall deposition issues in practical devices. The DAL HV-TFT with a 30-nm Al2O3 gate dielectric achieves a remarkable VBD of 450 V, the highest figure of merit of 118.2 kW/cm2, and a positive threshold voltage of 3.65 V. Both experiments and simulations indicate that the breakdown occurs within the semiconductor channel, paving the way for further improvement of the performance. [ABSTRACT FROM AUTHOR]

This paper presents a methodology for the physical analysis of defects on p-GaN power HEMTs that have been electrically stressed under DC surge or voltage switching stresses. The methodology includes a backside approach for sample preparation and defect localization. It is crucial to adapt the preparation process according to the position of the defect in the device structure (including metallurgy, dielectric layers, epitaxy, etc.), which depends on the type of stress applied. In our study of the reliability of the transistor under increased electrical stress in lifetime operation mode, failure analysis is used to identify the weakest areas in the design with respect to the type of stress applied. This paper presents a failure analysis consisting of techniques such as electrical characterization, photon emission microscopy and lock-in thermography for defect localization, focused ion beam slice and view, transmission electron microscopy analysis, and frontside conductive atomic force microscopy after immersion in hydrofluoric acid. [ABSTRACT FROM AUTHOR]

This paper introduces a novel differential combiner designed to effectively address parasitic capacitances of transistors used in power amplifier (PA) designs with precise compensation at a specified frequency. The combiner consists of a λ / 4 transmission line with an integrated capacitor of value 2 C O U T at its midpoint, which ensures accurate cancellation of parasitic effects. This design connects the drain pins of two transistors, which are considered identical in this configuration. By eliminating the need for complex parasitic compensation techniques, this method significantly simplifies the design process of Doherty Power Amplifiers (DPAs). Extensive simulations validate the effectiveness of this approach, highlighting its potential as a versatile and straightforward solution for next-generation communication systems. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The total ionizing dose effect of Mg-doped p-GaN gate stack have been investigated in this Letter on the whole gate voltage swing arranging from −1.3 to +1.5V. Additionally, two distinct kinds of mechanisms of trap effects have been extracted, which are response to in turns three phases of mechanism, voltage-controlled, coexist of voltage/current-controlled and current-controlled. It indicates that the fast traps are located at p-GaN/AlGaN interface (ET is about 0.295–0.333 eV), while the slow traps are located at AlGaN/GaN interface (ET is about 0.393–0.485 eV). They both have increasing trap density and broader range under γ-ray radiation. When the applied gate voltage rises to about 1 V, the effects of slow trap states are significantly weakened. However, the fast trap states barely change. Finally, the complete transition into current-controlled mode is observed at 1.5 V. What is more, p-GaN/AlGaN interface traps are further extracted near the gate turn-on voltage under γ-ray irradiation rather than the voltage-controlled mechanism of weak accumulation at the threshold voltage. Under the 600 krad γ-ray irradiation, the holes trap at p-GaN/AlGaN interface is identified with the trap activation energy ET at about 0.28–0.3 eV and trap density of about 4 × 1012 cm−2 eV−1. The increase in trap induces the reduction of gate current. In summary, this work can further our understanding of radiation tolerance and trapping effects of p-GaN gate high-electron mobility transistors for power switches, especially in regard to forward conduction status. [ABSTRACT FROM AUTHOR]

Active gate driving (AGD) is a promising concept for achieving high‐performance power transistor switching. This is particularly crucial for Silicon Carbide (SiC) MOSFETs since their inherently fast switching characteristics give rise to severe overshoots and oscillations which translate into increased levels of electromagnetic interference (EMI) emissions. In this paper, an AGD strategy using a single‐pulse applied during the switching transient is considered for a 1200 V 400 A SiC MOSFET module. The effect of single‐pulse timing, load current, and temperature on the switching performance is analyzed in detail. The radiated EMI reduction benefits are quantified by H‐field and E‐field probes. A conceptual closed‐loop AGD approach is presented and compared to open‐loop operation. For the transistor turn‐off case under full load current of 400 A, experimental results show that it is possible to reduce voltage overshoot by 43.3%, voltage and current oscillations by 69.7% and 52.2% respectively, and EMI by 76.6%, with a trade‐off in the switching energy by a relatively minor increase of 18.2%, compared to the conventional gate driving case. For the turn‐on case, current overshoot was reduced by 32.7%, EMI by 52%, voltage and current oscillations by 54.6% and 52.8%, respectively, with a penalty of 50.9% increase in the switching loss. [ABSTRACT FROM AUTHOR]

This work presents a sub-nanowatt voltage reference (VR) achieving a high-power supply ripple rejection (PSRR). It utilizes a self-current biasing circuit to reduce the voltage dependency of the output voltage (VREF) to the power supply variations. For low-power operation, all transistors operate in the subthreshold region. The design's performance is verified through post-layout and Monte Carlo simulations in a standard 180 nm CMOS process. Results show that the proposed bandgap achieves an output voltage of 0.150 V with a PSRR of -81.5 dB at Vdd = 1V. Notably, it eliminates the need for an additional startup circuit and consumes only 0.72 nW at T = 27°C with Vdd = 0.5V. The proposed voltage reference exhibits a temperature coefficient (TC) of approximately 18 ppm/°C over a temperature range of -20°C to 130°C while without using a trimming circuit a reasonable (σVREF/μVREF) = 2.3% is obtained. This design's average line sensitivity (LS) is 0.072%/V (Vdd = 0.5V to 1.8V). However, the PSRR and LS values are temperature-dependent. At the high temperature of 130°C (worst-case), the PSRR and LS degrade to approximately -80.45 dB and 0.084 %/V, respectively. The output noise at the frequency of 1 KHz is obtained as 167.34 nV/√ Hz. The proposed VR occupies a small active area of 513.5 μm2. [ABSTRACT FROM AUTHOR]

The conventional planar Metal-Oxide-Semiconductor FETs (MOSFETs) are being replaced with Fin Field-Effect Transistors (FinFETs) due to their improved ability to manage power dissipation, propagation delay, leakage current, and short channel effects. Process variability is an issue for planar MOSFETs, however the amount of dopant ions in FinFETs reduces device performance variability. In this study, a Static-Random Access Memory (SRAM) cell employing FinFET technology is designed using three MOS transistors. It is composed of two NMOS plus a single PMOS transistor. One NMOS acts as access transistor while the pull-up and pull-down functions are performed by remaining NMOS and PMOS transistors, respectively. The proposed SRAM cell is simulated using H-SPICE simulator and is compared with existing SRAM cell designs in terms delay, power consumption and transistor count. Performance analysis shows that the proposed SRAM Cell overcomes the constraint and achieves full swing storage of logic values between 0 and 1. This justifies the definition of static. Implementing a single-ended SRAM cell also has the benefit of simplifying the SRAM cell architecture, which also results in a reduction in area. [ABSTRACT FROM AUTHOR]

Adders and subtractors are essential to many integrated circuits (IC), including microprocessors, and micro controllers. However, using complementary metal oxide semiconductor (CMOS) and field effect transistor (FET) technology to make conventional adders and subtractors increased transistor count and power consumption. So, this effort begins with hybrid adder-subtractor designs using FinFET and graphene nano-ribbon FET(GnrFET) nano technologies. Initial development of an enhanced full adder with carry prediction (EFOCP) based on multiplexer logic with rapid carry-output selection reduced sum estimation delays. The considerable reduction in carry-output selection time led to this finding. The dynamic path auto-configurable adder (DPAA) selects high-speed and low-speed carry propagation channels using the EFOCP module. The DPAA was also used to create a two-complement based dynamic path auto-configurable subtractor (DPAS). Last, the dynamic path auto-configurable joint adder-subtractor (DPAJAS) combines DPAA and DPAS. Compared to existing approaches, the proposed DPAJAS design reduces Total Energy Consumption (TEC) by 23.3%, Total Path Delay (TPD) by 17.9%, and Carry Out Rise Delay by 18.2%. It also reduces Carry Out Fall Delay (COFD) by 19.4%, Sum Rise Delay (SRD) by 18.2%, and Sum Fall Delay by 18.3%. Finally, the proposed DPAJAS reduces Average Power Consumption (APC) 17.6%. These enhancements demonstrate the higher performance and efficiency of the proposed EFOCP, DPAA, DPAS, and DPAJAS designs. [ABSTRACT FROM AUTHOR]

This work presents a comparative study of a step-down converter controlled through the algorithm MPPT Perturb and Observe (P&O) with or without a fuzzy logic controller supplied by a photovoltaic system. This study aimed at increasing the quantity of electric energy taken over from the photovoltaic systems by the load through the DC-DC convertor. To follow up the maximum power point where the transfer is performed from the photovoltaic system to the load at maximum power, the Perturb and Observe (P&O) method was used. Two programs were elaborated in MATLAB-Simulink R2018a to control the buck convertor commanded through the P&O algorithm with or without a fuzzy logic controller. The analysis of the results showed that a higher quantity of energy is transferred from the source to the receptor circuit in the case of the buck convertor controlled through the P&O algorithm with a fuzzy logic controller. The P&O algorithm was implemented on an experimental stand at the Laboratory of Electrical Machinery and Drives of the Engineering Faculty in Bacau, with the help of a program issued in the Arduino IDE programming environment. The analysis of the results showed that for an increase in the power conveyed to the receptor circuit, there will also be an increase in the filling factor of the PWM signal that controls the power transistor in the structure of the DC-DC convertor. The P&O algorithm with a fuzzy logic controller may also be implemented in the DC-DC converters in the structure of the driving systems of electric vehicles. [ABSTRACT FROM AUTHOR]

Phase-locked loop systems (PLL) are widely used in control circuits of transistor resonant voltage inverters of induction heating installations. One of disadvantages of PLL systems is low speed, which is caused by the presence of a lowpass filter. This disadvantage is absent in self-oscillating systems, when the switching moment of the transistors is determined on each of half periods. At the same time, an asymmetry of half periods is possible, which is a significant disadvantage if there is a transformer at the output of the inverter. A self-oscillating digital control system for a resonant voltage inverter and equal half periods durations of the inverter output voltage has been developed. It can work with different methods of regulating the output current and allows to provide switching modes of transistors with minimal power losses. [ABSTRACT FROM AUTHOR]

The LM2990-integrated circuit family was among the first low-dropout voltage regulators to use a coupling diode to reduce a quiescent current. In certain conditions, the coupling diode, connected between the output terminal and the driver transistor collector contact, activates to supply the serial power transistor base current from the load. Nonetheless, an indirect characterization of the serial NPN transistor was affected, making it difficult to estimate its forward emitted current gain and a base current as a function of the absorbed total ionizing dose. The original SPICE simulation model had some limitations with generating the faithful simulation of radiation effects in samples supplied with a non-ideal voltage source. Therefore, a novel four-step computer simulation method was developed to specify bias and load conditions when the coupling diode reaction would not negatively affect the characterization of the serial power transistor. The previously reported method for estimating the serial transistor base current could be successfully used for dropout voltages that slightly exceed three equivalent diode voltage drops (that is, 2.4V) at the base-emitter junctions of the output amplifier transistors. [ABSTRACT FROM AUTHOR]

This paper proposes a new DC–DC bipolar resonance converter that combines a dual‐active‐bridge and a multi‐port resonance Buck‐Boost converter. This structure uses a resonance network between the input and output ports, which has the following advantages: it creates a constant current supply in the open‐loop mode; it keeps the current phase of the output ports constant under different loads; and it allows reversing the power from any output port by adjusting the phase shift of its switches, if the converter is connected to a DC microgrid. In this way, power can be exchanged among each of the output ports and input ports. The advantages of this converter are bidirectional power exchange, power exchange between output ports, soft switching, high efficiency, integration of transformer parasitic elements, and the modular capability to connect multiple resources at the input. Furthermore, the proposed structure of the bipolar converter has been implemented for verification purposes, and its results are presented in three modes: open loop, voltage control, and current control. Additionally, the results of different modes of power sharing and their bidirectionally are shown. [ABSTRACT FROM AUTHOR]

An adaptive high-efficiency light-emitting Diode (LED) backlight driver scheme has been proposed to address the issue of additional power loss caused by LED forward voltage variation. In this scheme, the peak current and the duty cycle of each LED channel are adjusted separately through an adaptive control algorithm to minimize the voltage drop on the linear current regulator (LCR) of each LED channel to reduce the excessive power loss in each LED channel and enhance the total power efficiency. A linear current regulator, suitable for adaptive control, is designed on a 0.18 μm 5V complementary metal-oxide-semiconductor (CMOS) process. Simulation results demonstrate that the linear current regulator can achieve a linearly adjustable channel current ranging from 0 to 48 mA with a current resolution of 0.2 mA. Across different process corners and temperatures, the maximum error for the full current range is less than 0.1%. The core area of chip layout is about 0.1 mm2. The complete driver prototype comprises the LCR chips, external power MOS transistors, digital module, and LED chains. The test results show that the power loss of the linear current regulator has been significantly reduced, and the power efficiency of each LED channel has been measured at around 98.1%. [ABSTRACT FROM AUTHOR]

Copyright of Electric Machines & Control / Dianji Yu Kongzhi Xuebao is the property of Electric Machines & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

A fast-switching low-loss field-stop insulated gate bipolar transistor with a dual control gate (DIGBT) of a semi-insulating polycrytalline silicon (SIPOS) material is proposed in this paper. Because the SIPOS has uniform high resistance, it has an approximate linear electric potential distribution. When DIGBT conducts, the higher electric potential on SIPOS causes the P-type drift region (P-drift) to generate an inversion layer of electrons, adjusting the number of carriers and making the generation of non-equilibrium carriers no longer dependent on the doping concentration in P-drift (Nd) but on the electric potential distribution on SIPOS. Therefore, it can solve the contradiction among the breakdown voltage, forward voltage drop [VCE(sat)], turn-off time (toff), and turn-off loss (Eoff) caused by the Nd. Through Technology Computer Aided Design (TCAD) simulation, the VCE(sat) of DIGBT is 30.6% lower than that of SJFS IGBT. Meanwhile, DIGBT reduces the toff by 62.8% while reducing the Eoff by 83.0% compared to SJFS IGBT. In addition, the static latch-up I–V and the forward biased safe operating area of the DIGBT have been significantly improved. This paper adjusts the number of carriers through the characteristics of SIPOS material, enabling the above-mentioned physical phenomena to be applied in insulated gate bipolar transistor power devices and achieving device performance breakthroughs. [ABSTRACT FROM AUTHOR]

Three‐phase ac choppers feature output voltage amplitude controllability and enable more compact system realizations compared to autotransformers. For the practical realization advantageously standard power transistor with unipolar voltage blocking capability such as MOSFETs can be employed as a naturally resulting offset voltage between the grid and the input‐stage starpoint ensures purely positive power transistor voltages. This offset voltage is, however, not strictly defined and may drift to higher voltage values, resulting in high power transistor voltage stresses and finally a potential overvoltage breakdown. Traditionally, the offset voltage drift is prevented by introducing discharge resistors across the input‐stage capacitors which, however, results in substantial ohmic losses. This paper analyzes the offset voltage formation in ac choppers and proposes a novel clamping modulation scheme which ensures a strictly defined and minimum time‐varying offset voltage without need for discharge resistors. Theoretical analyses and circuit simulations are finally experimentally verified with a 400 V (rms, line‐to‐line) 50 Hz grid connected three‐phase buck‐boost ac chopper with 3 kW rated power. [ABSTRACT FROM AUTHOR]

This paper presents the design of a synergistic arithmetic logic unit (SALU) that combines a complementary metal-oxide–semiconductor (CMOS) and memristors using the modified gate diffusion input (m_GDI) technique. The proposed design aims to reduce power consumption, delay, and the number of transistors, which are critical parameters in digital VLSI design. We have incorporated the m_GDI technique to implement the SALU, resulting in a lower number of transistors and reduced power consumption along with the delay and power delay product (PDP). The whole proposed architecture has been constructed using a basic m_GDI cell that consists of one p-type (pMOS) and two memristors. Combinational arithmetic circuits like full adder and full subtractor have been designed using the XOR-based m_GDI approach, and their performance will double that of current methods. A 1-to-8 de multiplexer circuit has also been utilized to perform 8 different operations for the ALU. Using Cadence Virtuoso tools in 45-nm technology, we have simulated the proposed design and evaluated its performance with existing designs. The proposed design has the potential to be a viable option for low-power and high-performance digital VLSI design applications. It delivers improved power, delay, and PDP characteristics while using fewer components. The power consumption, delay, and PDP of the proposed architecture are 9.71E−6 W, 2.141E−9 s, and 2.0789E−14 J, respectively. Furthermore, the design comprises just 33 pMOS transistors and 66 memristors, which is a lower count and unique combination in contrast to previous techniques. [ABSTRACT FROM AUTHOR]

[Display omitted] [ABSTRACT FROM AUTHOR]

This article presents a capacitor‐less low dropout (LDO) regulator with a high power supply rejection (PSR) for system‐on‐chip (SoC) applications. With the proposed adaptive bulk‐driven feedforward (ABDFF) technique, in which the ripples are injected adaptively to the bulk of power transistor, the LDO maintains a steady PSR enhancement in wide load conditions, and a lower quiescent current and faster load transient response are realized. Post‐layout simulation results show that the proposed LDO regulator achieves −75‐dB PSR at 1 MHz from 1 to 100 mA and 60‐fs figure of merit (FoM) with a 100‐pF load capacitor. [ABSTRACT FROM AUTHOR]

GaN-based vertical superjunction high electron mobility transistors (HEMT) are recent avenues for power transistors. In this work, an enhancement mode vertical superjunction GaN-HEMT with gradient doping (GDP-SJ HEMT) is proposed and analyzed. In the GDP-SJ HEMT, the n-pillar doping concentration increases in a gradient manner from top to bottom. Whereas the concentration of the p-pillar is uniform and equivalent to the doping of the middle of the n-pillar. By optimizing the device design and doping profile, the specific-on resistance (Ron,sp) of the device has been reduced from 5.0 mΩ-cm2 to 3.79 mΩ-cm2. To the best of our knowledge, the frequency performance of vertical SJ HEMT has not been documented in the literature. As a result, we also performed a frequency study. The cut-off frequency (fT) of the proposed device is 78 MHz and the maximum frequency (fMAX) is 71 MHz. The device optimization increases the fT by 89% i.e. 148 MHz and fMAX by 67% i.e. 119 MHz. [ABSTRACT FROM AUTHOR]

Advancements in electronic technology have led to the emergence of portable devices like smartphones and smartwatches. For these devices, low-power supply management systems are crucial. In this study, the LDO (low-drop) regulator is implemented with TSMC 0.18 um CMOS high-voltage process. This chip is designed based on multi-current mirror circuits to implement a level-shifting circuit for controlling the error amplifier. The new architecture is achieved using the structure of three low-voltage operational amplifiers. The gate voltage of the power transistor is precisely driven by the level-shifting circuit, eliminating the need for a voltage limiting circuit on the power MOS's Vgs, thus enhancing the response time. This chip incorporates a temperature protection circuit that controls the feedback circuit for high-voltage MOS components. When the temperature exceeds a predefined threshold, the output shuts down immediately. Experimental results demonstrate that this chip can output voltages ranging from 3 to 19 V when the input voltage ranges from 3.5 to 20 V. The chip achieves a maximum output current of 1A and a peak conversion efficiency of 89.94%. [ABSTRACT FROM AUTHOR]

SiC devices can enhance power conversion in electric vehicles. However, traditional soldering techniques are limited by their low melting temperatures. Therefore, we used pressureless Ag sintering to assemble a 1200 V/200 A SiC metal-oxide-semiconductor field-effect transistor power module and compared the long-term reliability, electrical properties, and driving performance of the module with those of a similar module assembled using the solder Sn-3.0Ag-0.5Cu (SAC305). To assess sinter joint reliability, we performed power cycling tests over two temperature ranges, 50–150°C and 50–175°C, for 15,000 cycles. Subsequently, we compared the breakdown voltage (BVDSS) and drain-source on-resistance (RDS(ON)) of the SiC power modules and performed cross-sectional analyses of the device bonding interfaces. No difference in BVDSS was found between the Ag-sintered and SAC305-soldered joints. However, the RDS(ON) exhibited minimal variation for the Ag-sintered module but significantly varied for the SAC305-soldered module, suggesting that the former better maintained its characteristics. Furthermore, the electrical characteristics of the SAC305-soldered module underwent more significant alterations with increasing temperature change during power cycling, indicating that cracks propagated throughout the SAC305 soldered joint over time. Therefore, Ag sintering was quantitatively validated as the superior die attachment technology compared to soldering for long-term reliability. [ABSTRACT FROM AUTHOR]

In this paper, a new frequency domain behavior model for radio frequency (RF) power transistors based on a hyper‐parameter optimized Gaussian process regression (GPR) method is presented. The chaos game optimization (CGO) algorithm is used to optimize GPR hyperparameters, resulting in the CGO‐GPR model. The basic theory as well as the details of the modeling process are presented. Validation of the model is conducted using a 10‐watt GaN power transistor. Compared to the standard GPR model, the proposed model achieved a significant improvement. Furthermore, the comparison with the particle swarm optimization (PSO) based GPR model (PSO‐GPR) showed that the proposed model allows achieving superior performance, thereby confirming the effectiveness of the developed modeling technique. [ABSTRACT FROM AUTHOR]

Ternary circuits are promising due to their lower interconnect complexity, storage requirement, and lesser pin count than binary circuits. The adder is one of the most important building blocks of a digital processor. This paper proposes carbon nanotube field effect transistor (CNTFET)-based 'exact' and 'approximate' ternary full adders (TFA). The CNTFET is attractive for realizing multi-valued logic (MVL)/ternary circuits because its threshold voltage can be changed by altering the diameter of its carbon nanotube (CNT). The exact ternary adders are realized using unary functions and multiplexers. The circuit size of only the 'Sum' block of a TFA is pruned in approximate ternary full adders by varying degrees for achieving superior performance in terms of transistor count, delay, and power consumption compared to the 'exact' TFAs. This performance gain in approximate TFAs is obtained at the cost of accuracy in some of the 'Sum' outputs. Circuits are simulated with HSPICE using a 32 nm CNTFET technology node at various supply voltages and temperatures. The proposed exact adders exhibit lower power consumption and transistor count, higher robustness, and lower power delay product (PDP) and energy delay product (EDP) than existing ternary adders. The improvement in PDP of the proposed exact TFAs varies from 20 to 96% compared to existing TFAs. The performance of the exact TFAs is then further improved by approximating its 'Sum' block in approximate TFAs. Image blending is used to demonstrate the effectiveness of approximate ternary adders in error-tolerant applications. [ABSTRACT FROM AUTHOR]

Cold metals with an energy gap around the Fermi level have been shown a great potential for reducing the power dissipation of transistors and diodes. However, only a limited number of 2D cold metals have been studied. In this work, we explored 3D cold metals through a systematic material search and found 252 types in the database. We performed first-principles calculations to investigate the conductance and work functions of 30 cold metals for material selection. Additionally, we studied the thermoelectric properties of four typical cold metals, which possess much larger Seebeck coefficients and figure-of-merits than conventional metals, by one and two orders of magnitude, respectively. Specifically, we constructed a monolayer MoS2 transistor with a cold metal contact of ZrRuSb. Our quantum transport simulations indicate that cold metal contacted MoS2 FETs exhibit a subthreshold swing smaller than 60 mV decade−1 over four decades, and on-state currents over 1 mA μm−1 are achieved at a supply voltage of 0.5 V. Our research provides a theoretical foundation and material basis for exploring 3D cold metals in developing electronic and thermoelectric devices. [ABSTRACT FROM AUTHOR]

This paper introduces an innovative Magnetic Switch (MFS) designed to control and alter magnetic flux within energy system components, offering an alternative to conventional power electronic devices. The MFS comprises a low-current control coil, a control core, and a high-density magnetic flux-carrying main core combined with a main coil energy system. In this novel magnetic configuration, when a low-power current excites the control coil, the magnetic flux in the main core (supplied by the main coil) decreases to nearly zero. Conversely, when the control coil disconnects from the power source, the magnetic flux within the main core attains its maximum value. This operation positions the MFS as a groundbreaking concept within magnetic-based energy systems, akin to transistors in power electronics. The main outcomes of the MFS concept are that it can vary the magnetic flux of the main core in the large range, and it is a fast magnetic switch with a simple and low power loss control circuit and an independent control coil from the main coil. Analytical studies thoroughly elucidate the performance and advantages of this proposed magnetic switch, substantiated by Finite Element Method simulations and experimental prototype outcomes. [ABSTRACT FROM AUTHOR]

The paper describes the results of investigations illustrating the influence of the method of determining the excess of junction temperature and the selection of a function approximating the thermometric characteristic used in the procedure of measuring thermal resistance of a power MOS transistor on the measurement results. The investigations involved the measurements made using an indirect electrical method. Three methods of determining the excess of junction temperature of the transistor are presented, using a linear function and nonlinear function approximating thermometric characteristics. The thermal resistance measurement results obtained using each of the considered methods were compared. The measurement error caused by the selection of the considered methods was also analyzed. [ABSTRACT FROM AUTHOR]

The switching control circuit in a DC to AC inverter is the critical part that is applied to control the power transistors insulated-gate bipolar transistor (IGBTs) and metal-oxide semiconductor field-effect transistor (MOSFETs). This paper proposes a high-performance and low-cost pulse width modulation (PWM) control signal with a 120° phase shift circuit for a twolevel three-phase inverter. Typically, a PWM signal with a 120° phase shift for three-phase inverters is generated with the help of analogue components with more complicated designs and power losses or by using a microcontroller with necessary programming or coding. The proposed solution is to design a 120° three-phase shift circuit based on D flip-flops and the 555-timer to generate the clock signal for the flip-flop input in addition to the dead-time control circuit. The proposed circuit is controlled by one square wave signal as an input signal to generate six output PWM control signals at 50 Hz to operate six MOSFETs in the three-phase inverter. Simulation results in power simulation software PSIM and PROTEUS simulation tools are used to verify the proposed circuit. Hardware implementation of the proposed circuit and three-phase inverter is carried out to validate the performance of the proposed design. [ABSTRACT FROM AUTHOR]

A nonlinear capacitance compensation technique is presented in this paper to enhance the linearity of a power amplifier (PA) in the GaN process. The method involves placing an MSM varactor device alongside the GaN HEMT device, which works as the amplifying unit such that the overall capacitance observed at the amplifier input is constant, thus improving linearity. This approach is a reliable and straightforward way to improve PA linearity in the GaN process. The proof-of-concept prototype in this study involves the fabrication of a PA device using a standard GaN HEMT process, which successfully integrates the proposed compensation technique and demonstrates excellent compatibility with existing processes. The prototype has a saturation output power of 18 dBm, a peak power-added efficiency of 51.8%, and a small signal gain of 15.5 dB at 1 GHz. The measured AM–PM distortion at the 5 dB compression point is reduced by more than 50% compared to that of an uncompensated device. Furthermore, the results of third-order intermodulation distortion demonstrate the effectiveness of the linearity enhancement concept, with values improved by more than 5 dB in the linear region compared to those of the uncompensated device. All of the results demonstrate the potential utility of this design approach for wireless communication applications. [ABSTRACT FROM AUTHOR]

This article presents a comprehensive comparative evaluation of a three-phase Three-Level (3L) Flying Capacitor Converter (FCC) and a Stacked Polyphase Bridge Inverter (SPBI), specifically a converter system formed by two Series-Stacked Two-Level three-phase Converters (2L-SSC), for the realization of a 7.5 kW Integrated Motor Drive (IMD) with a high short-term overload capability. The 2L-SSC requires a motor with two three-phase windings and a split DC-link, but uses standard six-switch, two-level transistor configurations. In contrast, the bridge legs of the 3L-FCC feature flying capacitors whose voltages must be actively balanced. Despite the 800 V DC-link voltage, both topologies employ the same set of 650 V GaN power transistors, i.e., the same total chip area, and if operated at the same switching frequency, show identical semiconductor losses. Electric Discharge Machining (EDM) damage of the motor bearings is a relevant issue caused by the common-mode (CM) voltages of the inverter stage. The high effective switching frequency of the 3L-FCC and the possibility of CM voltage canceling in the 2L-SSC facilitate mitigation of EDM by means of CM chokes, whereby a substantially smaller CM choke with lower losses suffices for the 2L-SSC; based on exemplary designs, the 2L-SSC features only about 75% of the total volume and 85% of the nominal losses of the 3L-FCC. If, alternatively, motor-friendliness is maximized by including DC-referenced sine-wave output filters, the 3L-FCC's higher effective switching frequency and the 2L-SSC's need for two sets of filters due to the dual-winding-set motor change the outcome. In this case, the 3L-FCC features only about 60% of the volume and only about 55% of the 2L-SSC's nominal losses. [ABSTRACT FROM AUTHOR]

A novel frequency domain behavioral modeling method for gallium‐nitride (GaN) devices is presented in this article. By utilizing a multi‐dimensional polynomial function, the proposed technique interpolates DC‐bias voltage and temperature based on the Canonical section‐wise piecewise linear (CSWPL) model framework. A detailed description of the model's theory is provided. With data from 10‐W GaN devices, the model was implemented in commercial software and validated through both DC and radio frequency (RF) tests. A robust predictive ability is demonstrated by the obtained results, thus proving the accuracy of the developed modeling method. This model is superior to the standard CSWPL model in that it is capable of predicting transistor behavior at different bias voltages and temperatures using a single set of parameters, thereby greatly reducing the complexity of the model and the time required for extraction. [ABSTRACT FROM AUTHOR]

This paper presents a novel poly‐harmonic distortion (PHD) model that incorporates the DC input and output bias voltages using Gaussian process regression (GPR). Simulation tests were conducted using a 10‐W gallium nitride (GaN) HEMT transistor from Wolfspeed, and the model implementation test was performed in the Keysight Advanced Design System environment. The results showed that the GPR‐based PHD model exhibited good performance in predicting both fundamental and harmonic behaviors over a wide range of bias variations with significant advantages over basic linear regression methods. Additionally, the model accurately predicted load‐pull simulations. The measurement test was conducted using a 6‐W GaN device, and the results showed a mean error of 2.22% and 4.54% for the fundamental and second harmonic of the reflected wave, respectively. [ABSTRACT FROM AUTHOR]

This study analyzed the efficiency impact of a MOSFET output parasitic capacitance ( C o s s ) on a full-bridge LLC DC/DC converter. The core of the converter was the control chip for a half-bridge LLC DC/DC converter, and the output signal of the chip controlled the first-arm power transistors of the primary side of the converter. The coupling transformer reversed the output signal to control the primary side of the second arm of the power transistor. The full-bridge converter comprises a half-bridge control chip that converts the high-voltage DC power supply to a low-voltage DC power supply, which is then synchronously rectified and supplied to the load. The primary side of the power transistor achieves a zero-voltage switching (ZVS) state through the resonance of the LLC converter. This design gives the converter high power density and a simple structure. Furthermore, to determine the appropriate output parasitic capacitance for improving converter efficiency, this study analyzed the effect of the output parasitic capacitance on the switching loss and conduction loss of the power transistor on the basis of the output parasitic capacitance of the primary-side power transistor. A 1200 W converter prototype was fabricated in this study, and when the output was 300 W, efficiency increased from 92.603% to 93.462%, a 0.859% increase. The empirical results verified the feasibility of the proposed theory. [ABSTRACT FROM AUTHOR]

In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18- μ m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25 mA in 500 ns edge-time for 140 pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response. [ABSTRACT FROM AUTHOR]