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49 results on '"Pailloncy, G."'

3. Dynamics of electric field screening in photoconductive THz sources with spatially patterned excitation

Author

Dambrine, G., Gloria, D., Scheer, P., Raynaud, C., Danneville, F., Lepilliet, S., Siligaris, A., Pailloncy, G., Martineau, B., Bouhana, E., and Valentin, R.

Subjects
ING-INF/01 Elettronica
Abstract

65nm n-MOSFETs show state-of-the-art cutoff frequency with ft =210 GHz and microwave low noise and high gain properties(NFmin= 0.8dB and Gass=17.3 dB at 12 GHz). As compared with the previous nodes, the high frequency properties of these MOSFETs continue to be in agreement with the downscaling trends.

Published
2005

4. Noise in SOI MOSFETs and gate-all-around transistors

Author

Iniguez, B., Lazaro, A., Hamid, H.A., Pailloncy, G., Dambrine, Gilles, Danneville, Francois, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2005

5. High frequency low noise potentialities of down to 65nm technology nodes MOSFETs

Author

Dambrine, G., Gloria, D., Scheer, P., Raynaud, C., François DANNEVILLE, Lepilliet, S., Siligaris, A., Pailloncy, G., Martineau, B., Bouhana, E., Valentin, R., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Cutoff frequency, [SPI]Engineering Sciences [physics], Microelectronics, MOSFET circuits, Microwave technology, Millimeter wave technology, Calibration, CMOS technology, Transconductance
Abstract

International audience; 65 nm n-MOSFETs show state-of-the-art cut-off frequency with f t = 210 GHz and microwave low noise and high gain properties (NF min = 0.8 dB and G ass = 17.3 dB at 12 GHz). As compared with the previous nodes, the high frequency properties of these MOSFETs continue to be in agreement with the downscaling trends.

Published
2005

6. Propriétés hyperfréquences et de bruit des filières conventionnelles de transistors MOS à grille sub-100 nm

Author

Pailloncy, G., Dambrine, G., Danneville, F., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2005

7. High frequency noise of SOI MOSFETs : performances and limitations

Author

Danneville, F., Pailloncy, G., Siligaris, A., Iniguez, B., Dambrine, G., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2005

8. Monte Carlo characterization of fabricated partially-depleted SOI MOSFETs : high-frequency performance

Author

Rengel, R., Martin, M.J., Pailloncy, G., Dambrine, Gilles, Danneville, Francois, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2005

9. RF and noise properties of SOI MOSFETs, including the influence of a direct tunneling gate current

Author

Danneville, F., Pailloncy, G., Dambrine, G., Iniguez, B., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2004

10. High frequency noise sources extraction in nanometric MOSFETs

Author

Danneville, Francois, Pailloncy, G., Dambrine, Gilles, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), and Sikula J., Levinshtein M.

Abstract

ISBN 1-4020-2169-0

Published
2004

11. Noise modeling and performance in 0.15 µm fully depleted SOI MOSFET

Author

Pailloncy, G., Iniguez, B., Dambrine, G., Dehan, M., Raskin, J.P., Matsuhashi, H., Delatte, P., Danneville, F., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2004

12. Modélisation de bruit et performances de MOSFETs SOI totalement désertés

Author

Pailloncy, G., Iniguez, B., Dambrine, G., Dehan, M., Raskin, J.P., Matsuhashi, H., Delatte, P., Danneville, F., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2004

13. Bruit haute fréquence dans les transistors MOS sur SOI : méthodes de caractérisations et de modélisations

Author

Pailloncy, G., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2004

15. High frequency noise sources extraction in nanometrique MOSFETs

Author

Danneville, F., Pailloncy, G., Dambrine, G., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2003

16. Impact of down scaling on high frequency noise performance of bulk and SOI MOSFETs

Author

Dambrine, G., Raynaud, C., Vanmackelberg, M., Danneville, F., Pailloncy, G., Lepilliet, S., Raskin, J.P., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2003

17. Noise modelling of 0.25 µm fully depleted SOI MOSFETs

Author

Pailloncy, G., Dambrine, Gilles, Danneville, Francois, Iniguez, B., Raskin, J.P., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2003

18. Modélisation de bruit pour des MOSFETs SOI 0,25 microns totalement désertés

Author

Pailloncy, G., Iniguez, B., Raskin, J.P., Dambrine, G., Danneville, F., Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)

Published
2003

19. Impact of Si substrate resistivity on the non-linear behaviour of RF CPW transmission lines

Author

UCL, Roda Neve, Cesar, Lederer, Dimitri, Pailloncy, G., Kerr, D.C., Gering, J.M., McKay, T.G., Carroll, M.S., Raskin, Jean-Pierre, 2008 European Microwave Integrated Circuit Conference (EuMIC), UCL, Roda Neve, Cesar, Lederer, Dimitri, Pailloncy, G., Kerr, D.C., Gering, J.M., McKay, T.G., Carroll, M.S., Raskin, Jean-Pierre, and 2008 European Microwave Integrated Circuit Conference (EuMIC)

Abstract

Non-linear behaviour of RF coplanar transmission lines is analyzed for various values of Si substrate resistivitiy. Based on small-signal measurements performed under different DC bias conditions, voltage dependent capacitance and conductance per unit length of the transmission line are extracted and compared for several silicon substrates. Harmonic distortion of large RF signal at 900 MHz along CPW lines is measured using a spectrum analyzer based setup as well as with a LSNA which gives us access to the phase of the harmonic components. For an input power of +25 dBm, the highest harmonic component (2/sup nd/) is as high as -15, -57, -37 and -63 dBm for resistivity substrates of 20, 500, 5 k and 2 k Omega -cm, respectively. A reduction of 45 and 15 dB for all harmonic components was obtained for the 5 and 2 k Omega -cm HR-Si substrates, respectively, when a trap-rich passivation layer was used at the Si/SiO/sub 2/ interface, and for both characterization setups. The impact of the resistivity value on signal distortion with its relation to the bias-dependence substrate characteristic and the efficiency of the trap mechanism of the passivation layer are for the first time introduced from experimental result considerations., Anglais

Published
2008

20. New de-embedding technique based on Cold-FET measurement

Author

UCL, Pailloncy, G., Raskin, Jean-Pierre, 1st European Microwave Integrated Circuits Conference, UCL, Pailloncy, G., Raskin, Jean-Pierre, and 1st European Microwave Integrated Circuits Conference

Abstract

In this paper, we present a new de-embedding technique which does not require any dedicated RF test structure. This leads to great reduction of surface area on the wafer. Furthermore, this technique allows us to break through the re-contacting and dispersion problems that might affect the RF performance accuracy of future devices., Anglais

Published
2006

21. On-wafer wideband characterization of advanced MOS devices

Author

UCL - FSA/ELEC - Département d'électricité, Lederer, Dimitri, Chung, Tsung Ming, Pailloncy, G., Raskin, Jean-Pierre, Union Radio-Scientifique Internationale (U.R.S.I.) Benelux Meeting, UCL - FSA/ELEC - Département d'électricité, Lederer, Dimitri, Chung, Tsung Ming, Pailloncy, G., Raskin, Jean-Pierre, and Union Radio-Scientifique Internationale (U.R.S.I.) Benelux Meeting

Published
2006

24. Impact of downscaling on high-frequency noise performance of bulk and SOI MOSFETs

Author

UCL, Pailloncy, G., Raynaud, C., Vanmackelberg, M, Danneville, F., Lepilliet, S, Raskin, Jean-Pierre, Dambrine, G., UCL, Pailloncy, G., Raynaud, C., Vanmackelberg, M, Danneville, F., Lepilliet, S, Raskin, Jean-Pierre, and Dambrine, G.

Abstract

Parameters limiting the improvement of high-frequency noise characteristics for deep-submicrometer MOSFETs with the downscaling process, of the channel gate length are analyzed experimentally and analytically. It is demonstrated that the intrinsic Pucel's noise P, R, and C parameters are not strongly modified by the device scaling. The limitation of the noise performance versus the downscaling process is mainly related to the frequency performance (f(max)) of the device. It is demonstrated that for MOSFETs with optimized source, drain, and gate accesses, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high-frequency noise performance of ultra deep-submicrometer MOSFETs.

Published
2004

25. Noise modeling in fully depleted SOI MOSFETs

Author

UCL, Pailloncy, G., Iniguez, B., Dambrine, G., Raskin, Jean-Pierre, Danneville, F., UCL, Pailloncy, G., Iniguez, B., Dambrine, G., Raskin, Jean-Pierre, and Danneville, F.

Abstract

In this paper, we are presenting a noise modeling technique in fully depleted (FD) SOI MOSFET. Starting from a physical compact model which allows us to capture the physics in such devices, an original microscopic noise model, suitable to calculate the noise performance of any field effect transistor, is developed. The method is applied to study the noise properties of FD SOI MOSFETs (0.25 mum physical gate length, 0.16 mum effective gate length); this includes a discussion at a microscopic level, the calculation of the usual P, R, C parameters (close to the device physics) and of the noise performances, taking into account extrinsic elements. To conclude, a discussion related to the noise performances as a function of the down-scaling is proposed. (C) 2004 Elsevier Ltd. All rights reserved.

Published
2004

26. Modélisation de bruit et performances de MOSFETs SOI totalement désertés

Author

UCL - FSA/ELEC - Département d'électricité, Pailloncy, G., Iniguez, B., Dambrine, G., Dehan, Morin, Raskin, Jean-Pierre, Workshop action spécifique bruit – Bruit en régime linéaire et non-linéaire dans les composants et circuits de télécommunications, UCL - FSA/ELEC - Département d'électricité, Pailloncy, G., Iniguez, B., Dambrine, G., Dehan, Morin, Raskin, Jean-Pierre, and Workshop action spécifique bruit – Bruit en régime linéaire et non-linéaire dans les composants et circuits de télécommunications

Published
2004

27. Impact of down scaling on high frequency noise performance of bulk and SOI MOSFETs

Author

UCL - FSA/ELEC - Département d'électricité, Dambrine, G., Raynaud, C., Vanmackelberg, M., Danneville, F., Pailloncy, G., Lepilliet, S., Raskin, Jean-Pierre, SPIE's 1st International Symposium on Fluctuations and Noise, UCL - FSA/ELEC - Département d'électricité, Dambrine, G., Raynaud, C., Vanmackelberg, M., Danneville, F., Pailloncy, G., Lepilliet, S., Raskin, Jean-Pierre, and SPIE's 1st International Symposium on Fluctuations and Noise

Abstract

Parameters limiting the improvement of high frequency characteristics for deep sub micron MOSFETs (bulk and SOI) with the downscaling process of the channel gate length are analyzed experimentally. The high frequency performances of MOSFETs are generally characterized by the specific transit frequencies ft, fmax. ft and/or fmax, what is the good factor of merit to quantify the performance of a transistor ft, which corresponds to the transit frequency (when the gain is equal to 1) of the current gain, is an interesting criterion for high speed digital applications (speed and high swing) while fmax, which is defined as the transit frequency of the unilateral power gain is the best criterion for analogue microwave applications (amplifier, oscillators, etc.). fmax corresponds also to the transit frequency of the maximum available power gain (MAG) that is a realistic parameter of the optimization of microwave amplifiers. Moreover, at the opposite of ft, fmax includes the contribution of the gate resistance, which degrades the high frequency noise performance. The different contributions of the extrinsic and intrinsic parameters on these transit frequencies will be detailed. We will support this analysis by experimental results obtained from several deep sub micron SOI and bulk MOSFETs technologies. We will focus essentially this presentation on the different technological ways of optimization on the high frequency performance of MOSFETs and particularly concerning its high frequency noise characteristics.

Published
2003

28. Noise modelling of 0.25 µm fully depleted SOI MOSFETs

Author

UCL - FSA/ELEC - Département d'électricité, Pailloncy, G., Dambrine, G., Danneville, F., Iniguez, B., Raskin, Jean-Pierre, 17th International Conference on Noise and Fluctuations – ICNF 2003, UCL - FSA/ELEC - Département d'électricité, Pailloncy, G., Dambrine, G., Danneville, F., Iniguez, B., Raskin, Jean-Pierre, and 17th International Conference on Noise and Fluctuations – ICNF 2003

Published
2003

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