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• An improved multi-timescale coordinated control strategy is proposed to be used in an integrated energy system. • A hybrid energy storage system is introduced into the system. • Operating costs and carbon emissions are considered as the optimization objectives. • General rules for sizing hybrid energy storage system are proposed in this paper. In view of the complex energy coupling and fluctuation of renewable energy sources in the integrated energy system, this paper proposes an improved multi-timescale coordinated control strategy for an integrated energy system (IES) with a hybrid energy storage system (HESS). The power response characteristics of various devices in IES at different time scales are analyzed which shows that the multi-timescale coordinated control method can be well coupled with the IES including HESS. The advantages of HESS over single energy storage system in stabilizing power fluctuation and extending energy storage life are compared and analyzed while the control method of supercapacitor under multi-time scale coordinated control strategy is proposed. The primary energy consumption, operating costs, carbon dioxide emissions and load shedding costs are considered the optimization objectives in the day-ahead rolling optimization stage according to the day-ahead forecast renewable energy (RE) data. In the intraday rolling adjusting stage, the proposed method can reduce the effect of the RE day-ahead forecasting errors to achieve the intraday energy scheduling balance and ensure the safe operation of the devices of IES. Considering the background of IES with a high proportion of renewable energy, this paper makes innovative use of the advantages of HESS to improve the power response characteristic of the system. The high-frequency part of RE is balanced by HESS in the real-time coordinated control stage. A typical structure of IES is applied and the simulation results are analyzed to show the performance of the proposed method in this paper. Moreover, general rules for sizing of HESS are also proposed. The influence of the hybrid energy storage capacity allocation ratio on battery capacity loss and carbon emission reduction is discussed. The Pareto front including the configuration and cost of supercapacitor has been obtained. As shown in the case, the application of HESS in the IES can improve the power response characteristic, extend the lithium-ion battery (LiB) life and has more benefits in reducing carbon emissions. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

The advent of multigate transistor technology for 20-nm technology node and beyond, has increased the importance of wire parasitics, in particular, wire resistance in determining the circuit delay computation. Variability in wire dimensions directly impacts the wire parasitics, hence, the overall system performance. For the first time, in this paper, we study circuit variability for 11- and 7-nm technology nodes based on GDSII-level layouts. We propose novel hybrid multipatterning flows, which combine the litho-etch-litho-etch and self-aligned-spacer technologies, to reduce circuit variability induced by the lithography process. We engineer the hybrid solutions to have reduced variability in wire resistance, and circuit performance, and develop variability models for each patterning proposal. We also find the increasing need of these hybrid solutions at the 7-nm technology node. For Extreme Ultraviolet (EUV) lithography to enable higher circuit performance than the proposed patterning regimes, it requires a high precision in core variation of less than 1 nm. [ABSTRACT FROM AUTHOR]

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law. For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- Vth optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power. [ABSTRACT FROM PUBLISHER]

Pruning is showing huge potential for compressing and accelerating deep neural networks by eliminating redundant parameters. Along with more terminal chips integrated with AI accelerators for internet of things (IoT) devices, structured pruning is gaining popularity with the edge computing research area. Different from filter pruning and group-wise pruning, stripe-wise pruning (SWP) conducts pruning at the level of stripes in each filter. By introducing filter skeleton (FS) to each stripe, the existing SWP method sets an absolute threshold for the values in FS and removes the stripes whose corresponding values in FS could not meet the threshold. Starting with investigation into the process of stripe wise convolution, we use the statistical properties of the weights located on each stripe to learn the importance between those stripes in a filter and remove stripes with low importance. Our pruned VGG-16 achieves the existing results by a fourfold reduction in parameter with only 0.4% decrease in accuracy. Results from comprehensive experiments on IoT devices are also presented. [ABSTRACT FROM AUTHOR]

This paper analyzes the impact of the interconnect variation at the system level in terms of clock frequency based on a fast and efficient system-level variation-aware design methodology. Various types of interconnect variations are compared, such as the critical dimension for line/core and spacer, etch, chemical mechanical polishing (CMP), and overlay variations. The $3 \sigma $ values for these independent variation values are extracted from various fabrication processes, including the litho-etch-litho-etch (LELE) double patterning, self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP). The results indicate that the impact of the interconnect variation on the clock frequency increases for a processor at a smaller technology node, especially for the CMP variation. For the impact of the combination of five sources of interconnect variations, the processor using the SADP performs the best. The overlay variation and the spacer variation have a larger impact on the LELE double patterning and the SAQP patterning techniques. Up to 8% and 16% of the frequency drops are observed based on $1\times $ and $2\times $ of the default $3 \sigma $ values, respectively. [ABSTRACT FROM PUBLISHER]

Based on realistic circuit- and system-level simulations, graphene interconnects are analyzed in terms of multiple material properties, such as the mean free path (MFP), the contact resistance, and the edge roughness. The benchmarking results indicate that the advantage of using graphene interconnects occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay product (EDP). At the circuit level, one representative circuit, a 32-bit adder, is investigated, where up to 40% and 70% improvements in delay and EDP are observed. At the system-level analysis, an ARM Cortex-M0 processor is synthesized, and placement and routing are performed. After replacing copper interconnects with multilayer graphene interconnects, up to 15% and 22% performance improvements in clock frequency and EDP have been observed. It is also demonstrated that the benefits of using graphene for the ARM core processor are strongly dependent on the quality of the graphene, such as the MFP and the edge roughness. [ABSTRACT FROM AUTHOR]

Despite the rapid development of photovoltaic (PV) industry, direct current (DC) fault arc remains a major threat to the safety of PV system and personnel. While extensive research on DC fault arc has been conducted, little attention has been paid to the long-time interactions between the PV system and DC arc. In this paper, a simulation system with an arc model and PV system model is built to overcome the inconvenience of the fault-arc experiments and understand the mechanism of these interactions. For this purpose, the characteristics of the series DC arc in a small grid-connected PV system are first investigated under uniform irradiance. Then, by comparing with different arc models, the Habedank model is selected to simulate the fault arc and a method to determine its parameters under DC arc condition is proposed. The trends of simulated arc waveforms are consistent with the measured data, whose fitting degree in adjusted R-squared is between 0.946 and 0.956. Finally, a phenomenon observed during the experiment, that the negative perturbation of the maximum power point tracking (MPPT) algorithm can reduce the arc current, is explained by the proposed model. [ABSTRACT FROM AUTHOR]

With the rapid development of the communication industry in the fifth generation and the advance towards the intelligent society of the sixth generation wireless networks, traditional methods are unable to meet the ever‐growing demands for higher data rates and improved quality of service. Deep learning (DL) has achieved unprecedented success in various fields such as computer vision, large language model processing, and speech recognition due to its powerful representation capabilities and computational convenience. It has also made significant progress in the communication field in meeting stringent demands and overcoming deficiencies in existing technologies. The main purpose of this article is to uncover the latest advancements in the field of DL‐based algorithm methods in the physical layer of wireless communication, introduce their potential applications in the next generation of communication mechanisms, and finally summarize the open research questions. [ABSTRACT FROM AUTHOR]

Beyond the 22-nm technology node, interconnect parasitics are increasingly contributing to the degradation of circuit performance. Thus, the focus is on optimizing interconnect parasitics in order to achieve optimum performance. The increased total device capacitance and the reduced device resistance of multigate transistors amplify the importance of wire resistance in circuit delay. In this paper, the impact of interconnect resistance on the circuit performance is weighed against interconnect capacitance, and less aggressive wire width and thickness scaling are proposed. This analysis is carried out based on the results from fully timing-closed, GDSII-level layout of circuit blocks, for the 11- and 7-nm technology nodes. The sensitivity of circuit power dissipation and signal noise to interconnect dimensions is assessed in detail. This approach compromises wire capacitance and gradually renders it important in circuit delay. The circuit performance enhancement by air-gap (AG) interconnect technology is studied with the traditional BEOL scaling versus the proposed wire sizing. It is found that using the latter wire sizing approach with air-gap interconnects is more beneficial to circuit performance. [ABSTRACT FROM PUBLISHER]

Promising interconnect materials continue to emerge and are considered as potential replacements for Cu interconnects. In this article, an interconnect technology/system codesign methodology is presented to efficiently optimize generic interconnects using ballistic materials. The key requirements of material-level characteristics to replace conventional Cu counterparts are quantified, such as the channel density, mean free path (MFP), and contact resistance. Furthermore, to achieve maximal chip-level throughput, two interconnect design schemes are proposed and optimized under a given number of metal layers, die area, and power density constraints. Results demonstrate that the optimal design scheme strongly depends on the power constraint, driving devices as well as material parameters, including the contact resistance. It is shown that up to 45% of the throughput improvement can be achieved by replacing both local and intermediate Cu interconnects at an ultralow-power budget. [ABSTRACT FROM AUTHOR]

As the traditional CMOS technology encounters significant scaling challenges, many emerging beyond-CMOS devices have been proposed and developed to augment or even replace CMOS devices. Spintronic devices have received extensive attention due to several unique attributes, including a low operation voltage and nonvolatility. However, spintronic devices are intrinsically slow because of the long switching delay of the magnet. To overcome the drawback, in this article, we propose and develop a deep pipeline method for generic spintronic majority-gate-based circuits. A fast and efficient pipeline buffer insertion methodology is integrated into the industry-standard placement and routing design flow to ensure the correct functionality. The proposed framework can accurately capture 1) the timing of a multiphase clock-gated spintronic circuit and 2) the energy overhead associated with the supply clocking, which is one major overhead of spintronic circuits. Based on the proposed framework, we demonstrate that a spintronic circuit implemented with a deep pipeline can provide over $10\times $ reduction in energy-delay products compared to their traditional CMOS-based counterparts. In the case study, the proposed deep pipeline method is applied to three emerging spintronic devices. Results show that device-level parameters have significant impacts on circuit-level performance and optimal logic depth. [ABSTRACT FROM AUTHOR]