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Herein, epitaxially regrown n+ (In)GaN source/drain layers for radio frequency high electron mobility transistors, addressing material and electrical characterization, are reported. A range of n+ GaN and n+ InGaN layers with indium 4–12 at% and silicon 0–5.1 × 1020 cm−3 are evaluated. The active carrier concentration in n+ InGaN exceeds 2 × 1020 cm−3. The layers exhibit so‐called V‐defects, observed by atomic force microscope and transmission electron microscope (TEM), which are associated with local composition changes. In addition to the high Si doping levels, nitrogen vacancies are also considered to contribute toward their net carrier concentration. Due to its relevance for device processing, selectivity analysis is performed, and the optimal process conditions for selective regrowth are identified. Regrowth under high temperature (800 °C) is found to be conducive to improved selectivity. However, a high thermal budget negatively impacts the overall regrowth process, as reported here for In0.17Al0.83N and Al0.26Ga0.74N barriers: whereas the InAlN barrier suffers from intermixing, the AlGaN barrier demonstrates high‐temperature stability. The impact of intermixing is studied from complementary TEM and DC electrical measurements. A low overall contact resistance of 75 Ω μm is obtained with the regrown n+ InGaN layers. [ABSTRACT FROM AUTHOR]

For operation as power amplifiers in RF applications, high electron mobility transistor (HEMT) structures are subjected to a range of bias conditions, applied at both the gate and drain terminals, as the device is biased from the OFF- to ON-state conditions. The stability of the device threshold voltage (Vt) condition is imperative from a circuit-design perspective and is the focus of this study, where stresses in both the ON and OFF states are explored. We see rapid positive threshold voltage increases under negative bias stress and subsequent recovery (i.e., Vt reduces), whereas conversely, we see a negative Vt shift under positive stress and Vt increase during the subsequent relaxation phase. These effects are correlated with the thickness of the GaN layer and ultimately result from the deep carbon-acceptor levels in the C-GaN back barrier incorporated to screen the buffer between the silicon substrate and the epitaxially grown GaN layer. Methods to mitigate this effect are explored, and the consequences are discussed. [ABSTRACT FROM AUTHOR]

We report a comprehensive analysis of the leakage current mechanism in ion implantation isolation (I/I/I) regions of GaN high electron mobility transistors. We applied a three-step high-energy low-dose N I/I/I to AlGaN/AlN/GaN heterostructures. High-quality isolation is achieved with isolation sheet resistances Rsh in the range of 1013–1015 Ω/sq. The analysis of isolated heterostructures with varied AlGaN or AlN thicknesses indicates common electron leakage paths at the surface of GaN. The electrostatics of the leakage path is determined by an interplay between the high densities of defects created by I/I/I, the net sheet polarization charges between III-nitrides, and the AlGaN surface states. We find that the activation energy of Rsh positively correlates with the energy level of the leakage path. The energy band diagram of the isolation region is constructed by correlating the activation energies of Rsh with the heteerostructure electrostatics. Moreover, our study makes a novel method to estimate the net active defect density caused by I/I/I: net active defect densities of ∼2 × 1019 and ∼2 × 1018 cm−3 are extracted in the GaN and AlGaN layers, respectively. [ABSTRACT FROM AUTHOR]

Boltzmann relations are widely used in semiconductor physics to express the charge-carrier densities as a function of the Fermi level and temperature. However, these simple exponential relations only apply to sharp band edges of the conduction and valence bands. In this article, we present a generalization of the Boltzmann relations accounting for exponential band tails. To this end, the required Fermi–Dirac integral is first recast as a Gauss hypergeometric function followed by a suitable transformation of that special function and a zeroth-order series expansion using the hypergeometric series. This results in simple relations for the electron and hole densities that each involve two exponentials. One exponential depends on the temperature and the other one on the band-tail parameter. The proposed relations tend to the Boltzmann relations if the band-tail parameters tend to zero. This work is timely for the modeling of semiconductor devices at cryogenic temperatures for large-scale quantum computing. [ABSTRACT FROM AUTHOR]

The radio-frequency noise performance of FinFETs from a 60-nm gate length is investigated. It is observed that the fringing capacitance of the 3-D and multifin structure of the FinFETS is responsible for the degradation of its noise performance.

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and Si[O.sub.2] with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeterwave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz. Index Terms--Electrostatic discharges (ESDs), fin-shaped fieldeffect transistor (FinFET), mixed analog integrated circuits, nanotechnology.

The effect of gate-length downscaling on the radio frequency (RF) performance of double-gate fin field-effect transistors (finFETs) is analyzed using TCAD simulations. The results have shown that the double-gate finFETs have the potential to reach the RF International Technology Roadmap for Semiconductor targets in the few decananometer regimes.

An approach based on the method of moments is presented for the computation of the sensitivity of infinite and finite receiving phased arrays with active beamforming networks. The sensitivity is characterized in terms of signal-to-noise element patterns. Coupling of noise through the array is included in the analysis, as well as noise resulting from losses in the antennas. Simulation results are shown for arrays consisting of tapered-slot antennas made of metallic plates. For finite arrays, the average signal-to-noise ratio per element is not necessarily smaller than in the infinite-arraycase. For an 8 x 8 array, the average signal-to-noise element pattern is somewhat more narrow than for the infinite array. At broadside, the sensitivity of relatively small arrays (4 x 4 to 8 x 8) is described within order 1 dB by the infinite-array solution. Index Terms--Noise, phased array, sensitivity.