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This paper presents the implementation of a low-power and variable-gain 60 GHz millimeter-wave CMOS Amplifier designed for short-range multi-gigabit close proximity point-to-point communications. The design uses coplanar wave transmission lines to achieve 50 Ω input and output matching. Realized in a 90 nm CMOS process, the variable-gain VGA exhibits power consumption ranging from 4.7 mW to 39.1 mW, with gains spanning from 5.5 dB to 12.4 dB at 60 GHz and a 3 dB bandwidth exceeding 14.4 GHz. Input and output return losses remain below –10 dB across the gain spectrum. Successful demonstration of gain controllability further validates the circuit's performance. The compact VGA die, inclusive of pads, has dimensions of 740 μm by 920 μm, thereby occupying a core area of 0.2 mm2. This design demonstrates the potential of low-power, high-performance VGAs in enhancing millimeter-wave communication systems. [ABSTRACT FROM AUTHOR]

This paper presents a 5G new radio (NR) FR2 beamforming system with an integrated transceiver module. A real-time operating module providing enhanced flexibility and capability has been proposed. The integrated RF beamforming system with an integrated transceiver module can be operated in 8Tx-8Rx mode configuration simultaneously. A series-fed structure 8 × 7 microstrip antenna array for compact size and improved directivity is employed in the RF beamforming module. The RF beamforming module incorporates a custom 28 GHz, eight-channel fully differential beamforming IC (BFIC). An eight-channel BFIC in a phased-array beamforming system offers advantages in terms of increased antenna density and improved beam steering precision. The RF beamforming module is integrated with an RF transceiver module that enables the simultaneous up-conversion and down-conversion of the baseband signal. The RF transmitter module consists of a transmitter, a receiver, a signal generator, a power supply, and a control unit. The RF beamforming system can scan horizontally from −50° to +50° with a step of 10°. To achieve an optimized beam pattern, a calibration was conducted. The transmit and receive conversion gain of around 20 dB is achieved with the transceiver module. To verify the communication performance of the manufactured integrated RF beamforming system, a real-time wireless video transmission/reception test was performed at a frequency of 28 GHz, and the video file was transmitted smoothly in real time without interruption within a range of ±50°. [ABSTRACT FROM AUTHOR]

A novel adaptive mesh generation technique for efficient electromagnetic simulation of radio-frequency integrated circuits (RFICs) is herein presented. By exploring the geometrical and physical characteristics of RFICs, some adaptive mesh treatments, such as mesh projection, edge refinement, via polymerization, etc., are utilized to improve the accuracy and efficiency of electromagnetic computations. For strong coupling structures, such as two conductors in close proximity for a relatively large area, a projection-based mesh scheme is introduced to improve the accuracy of numerical integration. Moreover, the current most likely concentrates near the edges of conductors due to the edge effect. To better model the edge effect, an edge refinement scheme is applied. For via arrays that appear common in RFICs, an automatic via aggregation approach is adopted to improve computational efficiency yet still keep good computational accuracy. Finally, some numerical examples are given to validate the computational accuracy and efficiency of the novel adaptive mesh generation technique. [ABSTRACT FROM AUTHOR]

In this paper, investigations on heat sink property of a 4x2 wideband dual linear polarized phased array antenna comprised of 3D metal printed all metallic radiators, serving also as heat sink, is presented for X-band frequency. Two single radiators, each with a height nearly equal to ${\lambda }$ /2 corresponding to center frequency (9.50 GHz), shaped intuitively and placed orthogonal to each other and surrounded by a metal ring of square cross-section with overall dimension of ${\lambda }/2\times {\lambda }$ /2, constitutes the dual linear polarized radiating element. Both radiators are fed by an orthogonal arrangement of stripline feeds through a trapezium shaped metal plate, which in turn helps to integrate the antenna aperture with the beamforming network (BFN). A set of via fences are placed beneath each antenna element, which work as a thermal path between the BFN and antenna aperture. This radiating element resembles heat fins, and designed to cover 8.5-11.5 GHz impedance bandwidth. Good radiation pattern with low cross-polarization is obtained over the entire bandwidth, while the peak broadside gain is varying between 14–11 dBi. Beam scans are viable ±50° in ${\varphi }=0^{0}$ plane and ±30° in ${\varphi }=90^{0}$ plane. The array antenna aperture is built using 3D metal printing technology. The BFN is comprised of commercial silicon Radio Frequency Integrated Circuit (RFIC) chips which have been integrated with the antenna aperture. A beamforming algorithm is applied through serial peripheral interface (SPI) controller to achieve beam steering during the measurement process. The temperature reduction of 60°C is achieved with the heat sink structure when the temperature distribution of BFN with and without heat sink are compared for the 4x2 array. The temperature of the heat sink antenna is only 41°C and the temperature distribution is validated with an infrared (IR) camera.

A Gilbert-cell mixer is designed for operation in cryogenic conditions ( - 196 ∘ C) using UMC 180 nm CMOS technology. The operating frequency is determined as 5 GHz. The proposed mixer achieves an IIP3 of 12.8 dBm, a 1-dB compression of 2.19 dBm, and a conversion gain of around 4 dB at - 196 ∘ C. The design performance has been compared with the outcomes acquired at room temperature. It is verified that cryogenic conditions enable higher linearity and lower noise figure that elevates the mixer design performance. [ABSTRACT FROM AUTHOR]

In this paper, a wide-band noise-canceling (NC) current conveyor (CC)-based CMOS low-noise amplifier (LNA) is presented. The circuit employs a CC-based approach to obtain wide-band input matching without the need for bulky inductances, allowing broadband performance with a very small area used. The NC technique is applied by subtracting the input transistor's noise contribution to the output and achieves a noise figure (NF) reduction from 4.8 dB to 3.2 dB. The NC LNA is implemented in a UMC 65-nm CMOS process and occupies an area of only 160 × 80 μm2. It achieves a stable frequency response from 0 to 6.2 GHz, a maximum gain of 15.3 dB, an input return loss (S11) < −10 dB, and a remarkable IIP3 of 7.6 dBm, while consuming 18.6 mW from a ±1.2 V DC supply. Comparisons with similar works prove the effectiveness of this new implementation, showing that the circuit obtains a noteworthy performance trade-off. [ABSTRACT FROM AUTHOR]

In this paper, we describe the design, layout, and performance of a 6-bit TTD (true time delay) chip operating over the entire band of 2–18 GHz. The 1.15 mm2 chip is implemented using TSMC foundry 65 nm technology. The least significant bit is 1 ps. The design is based on the concept of all-pass network with some modifications intended to reduce the number of unit cells. Thus, the first three bits are implemented in a single delay cell. A peaking buffer amplifier between bit 4 and bit 5 is used for impedance matching and partial compensation of the insertion loss slope. The rms delay error of the TTD is <1 ps over most of the frequency band and insertion loss is between 2.5 and 6.3 dB for all 64 states. [ABSTRACT FROM AUTHOR]

This work details the optimization and evaluation of a CMOS low-noise amplifier by developing a new algorithm for the g m / I D approach and combining with a modified figure of merit index method. The amplifier includes on-chip matching elements (such as IC inductors) for resonance at the targeted frequencies. The simulation results of the optimized LNA model showed scattering parameter S 21 = 19.91 dB, noise figure NF = 3.54 dB and excellent linearity for third-order intermodulation parameter IIP3 = 5.89 dBm for the targeted frequency of f 0 = 2.4 GHz. [ABSTRACT FROM AUTHOR]

Design and implementation of a W-band on-chip bowtie-shaped slot antenna fabricated in 180-nm BiCMOS process is presented, and its performance and limitations are discussed. This antenna has a measured impedance bandwidth (S11 < -10dB) across the W-band frequency range and a very wide gain bandwidth, making it a candidate for wideband applications. The measured gain for this antenna is 0-1 dBi at 94 GHz. This letter also analyzes the influence of the RF probe to the on-chip antenna performance. © 2002-2011 IEEE.

This paper presents theoretical analysis and design procedures for low noise amplifiers (LNAs) in advanced CMOS technologies. For demonstration, a 30‐GHz LNA designed for 5G millimeter‐wave communication systems was fabricated in a 65‐nm CMOS process. It provides a power gain of 22.6 dB with a noise figure of 3.2 dB while drawing 7.3 mW from a 1.2 V supply. [ABSTRACT FROM AUTHOR]

Design and implementation of a W-band on-chip bowtie-shaped slot antenna fabricated in 180-nm BiCMOS process is presented, and its performance and limitations are discussed. This antenna has a measured impedance bandwidth (S11 < -10dB) across the W-band frequency range and a very wide gain bandwidth, making it a candidate for wideband applications. The measured gain for this antenna is 0-1 dBi at 94 GHz. This letter also analyzes the influence of the RF probe to the on-chip antenna performance. © 2002-2011 IEEE.

A novel design for a fully on-chip antenna operating at 140 GHz that can be fabricated with standard CMOS technology is proposed. In addition to the traditional microstrip feeding, the slot antenna is backed with an extremely thin cavity formed by two CMOS inner metal layers and vias in between. The proposed cavity prevents radiation from going inside the lossy silicon substrate and enhances the radiation of the slot antenna. It is also shown that the antenna radiation is not affected significantly by other metallic parts on the chip. Good agreement is achieved between results from a frequency-domain solver, HFSS, and a time-domain solver, CST. The simulated gain is around -2 dBi, and the radiation efficiency is around 18%, despite ohmic losses enhanced by the extreme flatness. The input 10-dB bandwidth is around 5 GHz. The total area of this antenna is 1.2 × 0.6 mm2 (0.56 λ0 × 0.28 λ0 at 140 GHz). © 2006 IEEE.

This paper presents a quadruple-band low noise amplifier (LNA) which utilizes a differential pair common-source (CS) cascode amplifier to drive a LC-tank loading. The capacitors array are parallel with the LC-tank to implement the central frequency selection. The band-selection switch employs the binary voltage controlling to alter the equivalent capacitance of capacitors array of the loading LC-tank, which results in the central frequency of the LNA is switched. The body self-biasing technique is designed to minimize the noise contribution caused by the body effect of the MOS devices. In addition, the analysis of the transistors dimension ratio versus output referred 1-dB compression point (OP$_{1-dB}$ ) is presented to describe the design of the linearity optimization in CS cascode LNA. The |S21| is 16.8, 16.63, 16.78, 16.39 dB at 2.35, 2.4, 2.45, 2.55 GHz, respectively. The noise figure (NF) is under 2.75 dB between the quadruple-band mode. This proposed LNA is simulated by 55 nm RF CMOS process and consumes 3.75 mW excluding output buffer from 1.25 V supply.

A 55-65-GHz CMOS high power amplifier (PA) is designed with the help of a spirally folded 1:2 balun. By this size-folded balun, balance-unbalanced conversion and high-power combination are accomplished concurrently. Within the internal of PA, differential signal pairs benefit simplification of inter-stage matching topologies. The designed three-stage PA offers above 16.3-dB gain from 55.1 to 65.0 GHz. It is able to deliver 17.8-dBm output referred 1-dB compression point (P1 dB) and 22.2-dBm saturated output power (Psat) with a peak power-added efficiency of 10.9%.

A novel design for a fully on-chip antenna operating at 140 GHz that can be fabricated with standard CMOS technology is proposed. In addition to the traditional microstrip feeding, the slot antenna is backed with an extremely thin cavity formed by two CMOS inner metal layers and vias in between. The proposed cavity prevents radiation from going inside the lossy silicon substrate and enhances the radiation of the slot antenna. It is also shown that the antenna radiation is not affected significantly by other metallic parts on the chip. Good agreement is achieved between results from a frequency-domain solver, HFSS, and a time-domain solver, CST. The simulated gain is around -2 dBi, and the radiation efficiency is around 18%, despite ohmic losses enhanced by the extreme flatness. The input 10-dB bandwidth is around 5 GHz. The total area of this antenna is 1.2 × 0.6 mm2 (0.56 λ0 × 0.28 λ0 at 140 GHz). © 2006 IEEE.

A wideband LC-VCO IC with an Inversion-MOS (IMOS)-based novel varactor is proposed in this article. The novel varactor that consists of an IMOS and a fixed metal–insulator–metal (MIM) capacitor is able to provide a continuous tuning range with a single analog control voltage. The proposed VCO IC is designed, fabricated, and fully evaluated on the wafer in 40-nm CMOS SOI. The proposed wideband VCO IC has exhibited a tuning range of 40.3% from 4.14 to 6.23 GHz and a measured FoMT of −197.3 dBc/Hz under a supply voltage of only 0.34 V. [ABSTRACT FROM AUTHOR]

Quantum computers require classical electronics to ensure fault-tolerant operation. To address compactness and scalability, it was proposed to implement such electronics as integrated circuits operating at cryogenic temperatures close to those at which quantum bits (qubits) operate. Circulators are among the most common blocks used in the qubit readout chain, but they are currently discrete devices with a bulky footprint, thus preventing large-scale system integration. For this reason, we present here a detailed description of the first fully integrated CMOS circulator operating from 300 K down to 4.2 K to be an integral part of cryogenic quantum computing platforms. At 300 K, the circuit’s operating frequency is centered around 6.5 GHz with 28% fractional bandwidth, and it has 2.2-dB insertion loss, 2.4-dB noise figure, and 18-dB isolation while consuming 2.5-mW core power. These results are achieved thanks to a fully passive architecture based on $LC$ all-pass filters, which allows achieving a $1.6\times $ increase in fractional bandwidth and the lowest power consumption with respect to the state of the art while using only 0.45 mm2 of core area. This allows miniaturization of circulators in power-constrained multi-qubit readout systems. [ABSTRACT FROM AUTHOR]

A compact, flexible crossed-dipole circular polarized antenna using commercially available paper substrate is presented which caters North American frequency band. The crossed-dipoles have meandered lines for reduction of size as well as increased inductivity in the antenna. Dipoles have asymmetric T-shaped rectangular endings to provide the required compactness. Two semicircles are induced between the orthogonal dipoles and meandering matching structure to accomplish circular polarization excitation. Good impedance matching with the chip is achieved through a modified meander line matching structure. The proposed design dimensions are 32 × 32 × 0.4 mm3. Systematic analysis revealed the results comprising circular polarization 3dB-AR bandwidth of 11MHz (909–920 MHz) and power transmission coefficient bandwidth of 36MHz (900–936 MHz). Time delay between interrogating signal and backscattered signal is measured and relative distance is calculated. Linear Least Square (LLS) method is applied to approximate the position of tag in interrogation area. The proposed tag is placed at known locations and its position is measured to analyze accuracy of the method by simulating the positioning algorithm code in MATLAB. Six valid tag positions 0.5–2 m read range and 0°–150° angular resolution has been investigated.

INTRODUCTION: Multimedia Broadcast Multicast Service (MBMS) primarily targets broadcasting mobile television contents and video streaming services. Consumers worldwide are rapidly using Dual SIM Dual Standby (DSDS) device that utilizes a single common Radio Frequency Integrated Circuit (RFIC) for supporting more than one Subscriber Identity Module (SIM) cards. These two popular feature requirements are quite contrasting and pose a significant challenge to the design and implementation of User Equipment (UE) to achieve lossless MBMS video performance and Call connectivity Key Performance Indexes (KPIs).OBJECTIVE: This paper targets a cross-layer optimization merging the application-domain quality metrics to the modem level realization of the DSDS scheduler algorithm and enhances the performance.METHOD: The knowledge about the video quality metrics is used to design inputs to the modem scheduler and derive the packet loss thresholds that would be bearable to sustain the desired video quality.RESULTS: Simulation model is prepared based on configurations which are taken from real field values used in commercial network operations. Different configurations of the jitter buffer sizes are defined along with watermarks level to determine the buffer status and corresponding set of actions in terms of DSDS scheduler operation adaptation as a feedback. Based on experimentation, with buffer window of 50ms and 10 % FEC redundancy configuration, optimumperformance is determined when RFIC throttling with 25% RFIC rejection for paging occasions is applied. No adverse impact is seen on paging while packet loss performance is optimized.CONCLUSION: Performance of MBMS operation on DSDS device is considered in this paper. Proposed algorithm provides the guidelines for designing the RFIC scheduler for DSDS operation to achieve robust and enhanced MBMS video performance along with maintaining call connectivity KPIs.

Quality factor enhancement for inductor and transformer has been achieved by the techniques such as fabricating the inductor and transformer on a glass substrate having high resistivity and by fabricating the inductor far away the silicon substrate and within this distance use of air, high-resistive silicon and silicon nitride as cavity. The simulation results are obtained by using the tool ASITIC (analysis and simulation of inductor and transformer for integrated circuits). Inductor is a key component in radio frequency (RF)-based devices and shows poor RF characteristics when it is formed on a Si substrate chip. It happens because of substrate-based RF losses and parasitics arised due to inter spiral tracks. Fabrication of inductor and transformer on a glass substrate results in a high quality factor as well as high self-resonance frequency which shows good prospects in various radio frequency integrated circuits applications. [ABSTRACT FROM AUTHOR]

INTRODUCTION: Multimedia Broadcast Multicast Service (MBMS) primarily targets broadcasting mobile television contents and video streaming services. Consumers worldwide are rapidly using Dual SIM Dual Standby (DSDS) device that utilizes a single common Radio Frequency Integrated Circuit (RFIC) for supporting more than one Subscriber Identity Module (SIM) cards. These two popular feature requirements are quite contrasting and pose a significant challenge to the design and implementation of User Equipment (UE) to achieve lossless MBMS video performance and Call connectivity Key Performance Indexes (KPIs). OBJECTIVE: This paper targets a cross-layer optimization merging the application-domain quality metrics to the modem level realization of the DSDS scheduler algorithm and enhances the performance. METHOD: The knowledge about the video quality metrics is used to design inputs to the modem scheduler and derive the packet loss thresholds that would be bearable to sustain the desired video quality. RESULTS: Simulation model is prepared based on configurations which are taken from real field values used in commercial network operations. Different configurations of the jitter buffer sizes are defined along with watermarks level to determine the buffer status and corresponding set of actions in terms of DSDS scheduler operation adaptation as a feedback. Based on experimentation, with buffer window of 50ms and 10% FEC redundancy configuration, optimum performance is determined when RFIC throttling with 25% RFIC rejection for paging occasions is applied. No adverse impact is seen on paging while packet loss performance is optimized. CONCLUSION: Performance of MBMS operation on DSDS device is considered in this paper. Proposed algorithm provides the guidelines for designing the RFIC scheduler for DSDS operation to achieve robust and enhanced MBMS video performance along with maintaining call connectivity KPIs. [ABSTRACT FROM AUTHOR]

A design methodology for a compact millimeter-wave on-chip bandpass filter (BPF) is presented in this paper. Unlike the previously published works in the literature, the presented method is based on quasi-lumped elements, which consists of a resonator with enhanced self-coupling and metal–insulator–metal capacitors. Thus, this approach provides inherently compact designs comparing with the conventional distributed elements-based ones. To fully understand the insight of the approach, simplified LC-equivalent circuit models are developed. To further demonstrate the feasibility of using this approach in practice, the resonator and two compact BPFs are designed using the presented models. All three designs are fabricated in a standard 0.13- $\mu \text{m}$ (Bi)-CMOS technology. The measured results show that the resonator can generate a notch at 47 GHz with the attenuation better than 28 dB due to the enhanced self-coupling. The chip size, excluding the pads, is only $0.096 \times 0.294$ mm2. In addition, using the resonator for BPF designs, the first BPF has one transmission zero at 58 GHz with a peak attenuation of 23 dB. The center frequency of this filter is 27 GHz with an insertion loss of 2.5 dB, while the return loss is better than 10 dB from 26 to 31 GHz. The second BPF has two transmission zeros, and a minimum insertion loss of 3.5 dB is found at 29 GHz, while the return loss is better than 10 dB from 26 GHz to 34 GHz. Also, more than 20-dB stopband attenuation is achieved from dc to 20.5 GHz and from 48 to 67 GHz. The chip sizes of these two BPFs, excluding the pads, are only $0.076\times 0.296$ mm2 and $0.096\times 0.296$ mm2, respectively. [ABSTRACT FROM AUTHOR]

BiCMOS processes provide not only standard NMOS devices, but also high‐performance SiGe HBTs, facilitating simultaneous use of both NMOS and HBT. This article adopts the advantages of both HBT and NMOS to achieve a high‐gain, high‐power, and efficient power amplifier (PA). Through an analysis of cascode amplifiers implementing different combinations of HBT and NMOS, a high‐performance 28‐GHz BiCMOS PA, which combines both HBT and body‐floating NMOS strengths to achieve 15.7‐dB gain, 19.6‐dBm saturated output power (Psat), 17.5‐dBm output 1‐dB compression (OP1dB), and 28.8% maximum PAE, is proposed for 5G applications. [ABSTRACT FROM AUTHOR]

A high output power fully integrated V-band power amplifier (PA) is developed using a 0.18- $\ {\mu }\text{m}$ SiGe BiCMOS technology. The developed PA makes use of four-way parallel power dividing and combining structures to feed and combine powers from four identical unit-PA cells, respectively. Especially, the parallel power combiner and divider are developed by integrating a low-loss wideband Wilkinson structure and two transformers connected in parallel, which achieve broad bandwidth and minimum phase and amplitude mismatches between ports. The unit-PA is designed as a pseudo-differential two-stage cascode amplifier, which employ transformers for both matching and impedance transformation. The PA achieves measured broadband small-signal gain of 19 dB at 60 GHz and 3-dB bandwidth of 56.8–67.5 GHz, which encompasses the overall unlicensed V-band spectrum (57–64 GHz). In addition, it delivers 18.8 dBm of saturated output power and 15.3 dBm of output 1-dB compressed power at 60 GHz. Across 55 to 65 GHz, the PA achieves a very flat power performance with maximum output power between 17–19.1 dBm. [ABSTRACT FROM AUTHOR]

Abstract: A new wideband 0.18‐μm SiGe BiCMOS power amplifier (PA) operating from 16.5 to 25.5 GHz is presented. The PA consists of a drive amplifier and two main amplifiers integrated through lumped‐element Wilkinson power divider and combiner. The PA exploits the advantages of both HBT and NMOS characteristics in a cascode topology in addition to floating the NMOS body to achieve good gain, output power, power‐aided efficiency (PAE), and linearity. The developed PA has relatively flat saturated output power (Psat) of 18.5‐20.8 dBm, output 1‐dB compression point (OP1dB) of 15.1‐18.1 dBm, 13.5‐23% maximum PAE, and gain of 19.5 ±1.5 dB across 16.5‐25.5 GHz. At 24 GHz, the PA achieves Psat, OP1dB, maximum PAE, and gain of 20.8 dBm, 18.1 dBm, 23%, and 20 dB, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a scalable lumped model that accurately predicts the steady-state high-frequency behavior of nanoscale RF memristive devices is presented. The model is described 1) analytically by a set of closed-form equations that determine the parameters based on the device physical structure, allowing for optimized circuit design and performance through structure modifications, and 2) numerically to fit the model parameters to experimental data, allowing for evaluation of the accuracy of the model. This model is, to the best of our knowledge, the first lumped RF memristor model that includes device parasitics obtained from empirical measurements reported in the literature. Results show that the model is reasonably accurate, with 9.6% and 13% relative RMS error for the on-state magnitude and phase, respectively. Furthermore, we propose three topologies (series, shunt, and series-shunt) of nonvolatile single-pole double-throw switches using our lumped RF memristor model. The series and shunt topologies are single-voltage-controlled, while the series-shunt requires two control signals. Simulation results of these topologies exhibit low insertion loss and high isolation (below 0.25 dB and over 63 dB, respectively). The added nonvolatility and nanoscale size will result in reduced power consumption and higher density devices. [ABSTRACT FROM AUTHOR]

Abstract: A K‐/Ka‐band concurrent dual‐band low‐noise amplifier (LNA) employing an inductor feedback dual‐band load is presented. The dual‐band LNA can control the passband gain and stopband rejection performances to overcome the gain and notch performance degradation from process variations by adjusting the bias level of the second‐stage's inverting amplifier. The concurrent dual‐band LNA achieves peak gains of 21.3/23.2 dB at 21.5/36.5 GHz, respectively, and best noise figures of 2.6/2.5 dB at the low/high passbands, respectively. The dual‐band LNA exhibits the best noise figure and gain‐balance performances as compared to those operating at similar frequencies. [ABSTRACT FROM AUTHOR]

In this Letter, a flexible approach for low-loss on-chip bandpass filter (BPF) design in CMOS technology is presented. The proposed approach takes the advantages of a combination of an edge-coupled electromagnetic structure, namely resonator, and a pair of metal–insulator–metal capacitors for BPF implementation. To demonstrate the insight of the approach, the designed resonator is analyzed in details by means of a simplified equivalent LC-circuit model. Then, the impact on the BPF design due to the variations of the feeding capacitance is investigated. To prove the concept, both the resonator and BPF are fabricated in a standard 0.13- \mu \textm CMOS technology. The measured results show that the designed resonator can generate a notch with 20-dB attenuation at 59.4 GHz, while the BPF has a center frequency of 35.4 GHz with an insertion loss of 1.7 dB. The chip size of both devices, excluding the test pads, is only 0.039 mm2 ( $0.15 \times 0.26$ mm2). [ABSTRACT FROM PUBLISHER]

Abstract: A fully integrated wideband concurrent dual‐band single‐pole double‐throw (SPDT) switch with integrated dual‐band band‐pass filtering has been developed over two wide bandwidths around 24 and 60 GHz in a 0.18‐µm SiGe BiCMOS process. The developed concurrent dual‐wideband SPDT switch is configured to make it approximately equivalent to a dual‐band resonator in the on‐state operation. It exhibits measured insertion losses and isolations of 5.4 and 31.4 dB, and 5.2 and 16.5 dB at 24 and 60 GHz, respectively. The measured peak stop‐band rejection between the two pass‐bands is 26 dB at 42.3 GHz. With single‐tone 24‐ or 60‐GHz input, the measured input 1‐dB compression points (P1dB) are 20.4 and 17.1 dBm at 24 and 60 GHz, respectively. For concurrent dual‐tone 24‐ and 60‐GHz input, the measured input P1dBs are 17 and 14.5 dBm at 24 and 60 GHz, respectively. The measured input third‐order intercept points are 29.4 and 26.8 dBm at 24 and 60 GHz, respectively. [ABSTRACT FROM AUTHOR]

This letter proposes a compact and broadband quadrature coupler with a center frequency of 55 GHz, which consists of a 90° broadside coupled-line to support the differential signal propagation and two T-type L-C networks to support the common signal propagation. To analyze the proposed coupler, an equivalent circuit model is provided for estimation of the distributed and lumped component values. The measured results of the proposed on-chip quadrature coupler show that the return loss and isolation are greater than 20 dB with a bandwidth of 105%, while the insertion loss is about −0.85 dB. The magnitude imbalances are less than 1 dB within the bandwidth of 56% and the phase differences are with ±1° errors within the bandwidth of 96.9%. The chip size, excluding the test pads, is only $0.31\times0.22$ mm2. [ABSTRACT FROM AUTHOR]