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High Performance Computing (HPC) Systems are usually large systems which require specialized infrastructure. For a variety of small time users, who need performance of the parallel computing for their applications, such systems are unaffordable and inaccessible for a number of reasons. Even to setup a small state-of-the-art HPC system, such users would require vast efforts and expertise to design system specifications and to identify and install system software, tools and user applications. Also, going through such process would consume time and can be expensive. Clearly, there is a requirement of a small and low-cost ready-to- use HPC system which can be straightway put to utilization by end-users. In this paper, we present a case of a small, affordable and personalized supercomputing solution named PARAM Shavak [8, 9] which offers ready-to-use supercomputing-in-a-box solution based on commercial off-the-shelf HPC hardware resources. This solution is aimed as a support tool for research, design and development — often related to the education or small time designers. The solution is so architected that it provides scalability and power efficiency. We also discuss the uniqueness of our solution compared to several related initiatives which have been around and show its efficacy.

Ubiquitous availability and need for transparent remote data access has increased significantly due to increased capacity and widespread availability of computer networks such as Internet. Remote access can be facilitated by storing data at the file server and accessing data as required using distributed file systems (DFS's). This remote access exposes file server, client and data to various on-line and off-line attacks. Off-line attacks to data can be prevented by using Encrypting File System (EFS) such as TransCrypt [1], NCryptfs [2], Microsoft EFS [3], etc. On-line attacks can be handled by using dynamic security mechanisms such as mutual authentication and secure session establishment. In this paper, a secure DFS for providing access to data residing on a TransCrypt [1] server from a client machine is proposed. The proposed DFS is implemented, and can be used transparently and flexibly without requiring any change to the existing applications.

With the advent of the e-commerce, it has become much easier for a ‘data bandit’ to sit in non descriptive location and quietly siphon away money from the service users. The financial service outlets (e.g. automated teller machine (ATM), point of sale (PoS) terminal) have been a soft target for these bandits since long. In the existing model, the users are forced to trust a service outlet to be authentic. A spoofed outlet can collect the account information and use it in some way later. Installing an outlet is also an expensive affair due to the need of dedicated network connectivity. In this paper, we propose a model that would overcome these security and cost related issues of the conventional Financial Service Model. In developing economies, where two-third of the population still lives in rural areas with limited or no network connectivity, this model can help the banks reach the masses and foster economic growth.

Radio frequency identification (RFID) based system are expected to be deployed in a considerable manner in the near future. One of the crucial requirements for such vast deployment is the need for a scalable, robust and a in-complex software system to interface various RFID hardware with the RFID applications. In this paper, we present SmartRF, an RFID middleware which is flexible, simple and scalable. SmartRF allows usto interface RFID tags and readers to multiple applications in a technology-neutral (protocols, air-interface, etc.) manner. The object-oriented and layered design of SmartRF allows development and integration of new features with little effort. The middleware provides the application a flexibility to interact with one or more readers or even part of a reader. SmartRF supports dynamic joining and dis-joining of applications and hardware.We also present a generic application framework which helps in designing complex applications with ease. Two case studies - electronic file tracking and postal bag tracking which have been developed using SmartRF and the application framework are presented in the paper.

A person usually carries multiple authentication tokens in the form of various cards to access services electronically. Often the service outlets are equipped with a strong infrastructure to permit the user interactions. The network connectivity is usually a must for the service outlet to authenticate the user with the server. In this paper, we propose a solution which uses the personal mobile devices held by the user to interact with the service outlets. Such a system can then alleviate the needs for interaction console and communication infrastructure at service outlets.

The routing of nets or a set of interconnection points is a complete intensive application encountered in CAD for VLSI design. This paper proposes a gridless algorithm for area routing based on the Hightower's Maze routing algorithm for message passing multiprocessor systems. The suitability of k-d trees as a data structuring technique for gridless maze routing is established. Since segments of routes are stored as rectangular objects in the k-d tree, the algorithm facilitates routing with variable width conductor paths. Results obtained both through simulation techniques and those obtained on an actual multiprocessor system based on message passing exhibit speedup proportional to the number of processors in the multiprocessor system.

In this paper, we describe a Broadcast Cube System [BCS] architecture for high speed scientific computation and logic programming. The architecture is based on multiple fully connected broadcast networks connected in cube topology. We also present the software environment for the above architecture which supports multi-processing in a way which is very similar to the multiprocessing in UNIX operating system. A numerical integration program is also given in this paper which uses the subroutine calls from the software environment and runs on BCS architecture.

High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in languages like C, C++ or their variants. The generated RTL is described in a hardware specification language like VHDL or Verilog. The size of the variables specified in the algorithm has a significant impact on the area of the generated hardware. The language accepted by the high level synthesis tools typically allow the size or bit width of a variable to be specified explicitly. This paper describes a method to automatically determine the minimum bit width of the variables from a performance profile. This would be effective to reduce the combinatorial and the non-combinatorial area of the generated hardware.

The demands on embedded processors are growing faster than CPU developers can respond. This has lead to a number of academic and commercial processors, such as Tensilica (Leibson, 2003) and ARC, which allow hardware extensions in the form of new instructions to improve the overall throughput. Unfortunately, it is rarely obvious at the application level which new instruction would accelerate a given function. This paper proposes a design flow that migrates performance critical sections of software into hardware by automatically creating application specific hardware blocks that accelerate the overall software execution. The hardware implementation of the function is interfaced to the general-purpose processor, which runs the remainder of the software. Targeting FPGA fabric maintains the reprogrammable nature of the algorithm that was originally in software. We present our results on using this flow on the G.729 audio encoding algorithm.

The design of modern complex embedded systems require a high level of abstraction of the design. The Sim-nML is a specification language to model processors for such designs. Several software generation tools have been developed that take ISA specifications in Sim-nML as input. In this paper we present a tool Sim-HS that implements high level behavioral and structural synthesis of processors from their ISA specifications in Sim-nML. Behavioral Sim-HS transforms Sim-nML specifications of a processor to the corresponding behavioral Verilog model that is suitable for fast functional simulation. Structural Sim-HS generates structural synthesizable Verilog processor model from its Sim-nML specifications.

Reducing processor memory speed gap is one of the major challenges computer architects face today. Efficient use of CPU registers reduces the number of memory accesses. However, registers do incur extra overhead of load/store, register allocation and saving of register context across procedure calls. Caches however do not have any such overheads and cache technology has matured to the extent that today the access time of on-chip cache is almost equal to that of registers. This motivates one to explore alternate ways to do away with the overheads of registers. We propose a registerless, memory to memory architecture of a processor. We call this architecture Performance Enhanced Registerless (PERL) processor. All instructions in this processor operate directly on memory operands thus eliminating the load/store and other overheads of registers. The performance of this machine is studied by simulations and results are reported in the paper.

The current embedded systems design typically also involves the design of application specific integrated processors. In such scenarios, the designer needs to study various designs for choosing the best suited one with respect to the performance and the cost. The use of high level processor models along with automated tools is becoming popular in the performance study of the designs. This work involves the design and implementation of a Retargetable Functional Simulator Generator (RFSG) which is capable of generating a functional simulator for a processor given its high level model in the Sim-nML language and a binary for the processor in ELF format. The functional simulator so generated simulates the binary program for the described processor on any other host. It can also produce an uncompressed instruction trace for the binary program.

This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a generic way. The processor models are written in a language called Sim-nML which is powerful enough to capture the instruction set architecture of a processor We describe a few tools in this paper which can be retargeted to any processor using the high level Sim-nML model of the processor.

A software environment for general purpose multiple instruction multiple data (MIMD) machines based on packet switched message passing paradigms is described. The environment provides system calls for communication between various processing elements in the machine and system calls to get the configuration of the system. It assumes the presence of a host processor through which facilities are provided for forking remote processes on various processing elements. The host processor has all the peripherals of the system and acts as an I/O processor of the system. During the normal course of execution, it forks processes, collects results from various processing elements, sequences them and then produces the output of the program. >

Part 2: Short Papers; International audience; In this position paper we examine some of the aspects of trust models, deployment, use and ‘misuse,’ and present a manifesto for the application of computational trust in sociotechnical systems. Computational Trust formalizes the trust processes in humans in order to allow artificial systems to better make decisions or give better advice. This is because trust is flexible, readily understood, and relatively robust. Since its introduction in the early ’90s, it has gained in popularity because of these characteristics. However, what it has oftentimes lost is understandability. We argue that one of the original purposes of computational trust reasoning was the human element - the involvement of humans in the process of decision making for tools, importantly at the basic level of understanding why the tools made the decisions they did. The proliferation of ever more complex models may serve to increase the robustness of trust management in the face of attack, but does little to help mere humans either understand or, if necessary, intervene when the trust models fail or cannot arrive at a sensible decision.

Part 1: Full Papers; International audience; The prediction of the rating that a user is likely to give to an item, can be derived from the ratings of other items given by other users, through collaborative filtering (CF). However, CF raises concerns about the privacy of the individual user’s rating data. To deal with this, several privacy-preserving CF schemes have been proposed. However, they are all limited either in terms of efficiency or privacy when deployed on the cloud. Due to its simplicity, Lemire and MacLachlan’s weighted Slope One predictor is very well suited to the cloud. Our key insight is that, the Slope One predictor, being an invertible affine transformation, is robust to certain types of noise. We exploit this fact to propose a random perturbation based privacy preserving collaborative filtering scheme. Our evaluation shows that the proposed scheme is both efficient and preserves privacy.

Part 2: Short Papers; International audience; Museums are rapidly digitizing their collections, and face a huge challenge to annotate every digitized artifact in store. Therefore they are opening up their archives for receiving annotations from experts world-wide. This paper presents an architecture for choosing the most eligible set of annotators for a given artifact, based on semantic relatedness measures between the subject matter of the artifact and topics of expertise of the annotators. We also employ mechanisms for evaluating the quality of provided annotations, and constantly manage and update the trust, reputation and expertise information of registered annotators.

Part 1: Full Papers; International audience; Trust transitivity is a common phenomenon embedded in human reasoning about trust. Given a specific context or purpose, trust transitivity is often manifested through the humans’ intuition to rely on the recommendations of a trustworthy advisor about another entity that the advisor recommends. Although this simple principle has been formalised in various ways for many trust and reputation systems, there is no real or physical basis for trust transitivity to be directly translated into a mathematical model. In that sense, all mathematical operators for trust transitivity proposed in the literature must be considered ad hoc; they represent attempts to model a very complex human phenomenon as if it were lendable to analysis by the laws of physics. Considering this nature of human trust transitivity in reality, any simple mathematical model will essentially have rather poor predictive power. In this paper, we propose a new interpretation of trust transitivity that is radically different from those described in the literature so far. More specifically, we consider recommendations from an advisor as evidence that the relying party will use as input arguments in conditional reasoning models for assessing hypotheses about the trust target. The proposed model of conditional trust transitivity is based on the framework of subjective logic.