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Fast speed of read operation and stability is the general need of memory device, SRAM read stability can be achieved by keeping high ION/IOFF ratio. In this paper we propose a 8T SRAM Cell that results in reduction of Read delay and increase the ION/IOFF ratio at the same time in comparison with conventional 6T SRAM Cell and 7T SRAM Cell at the cost of leakage power. This paper is aimed to increase ION/IOFF ratio while keeping the faster Read speed. [ABSTRACT FROM AUTHOR]

SRAM Memory cell stability is a critical issue in scales technology. Memory cell suffered from the low stability problem at nanometer technology. Stability of memory cell against noise generally measured by a parameter called SNM. This paper analyzes read operation in static noise margin (SNM) of 6T SRAM cell and presents its stability variation with cell ratio (CR), pull-up-ratio (PR), temperature and power supply at 32nm and 45nm CMOS technology. This work uses a most popular butterfly method for SNM calculation of 6T memory cell. Simulation result indicates that the read SNM was 0.226v at nominal supply with a minimum size transistor in 45nm technology, which was 58% higher than 32nm technology in conventional 6T SRAM memory cell. The experimental results indicate that the value of SNM is reduced as technology scale down in 6T SRAM cell. Simulation was performed by Hspice using 32 nm and 45 nm PTM model. [ABSTRACT FROM AUTHOR]

Non-rcgcnerative circuits have vast utilizations in various electronic devices, computing devices and memory devices. There are various circuit designs to instrument a given logic function. The parameter that is dominant in high performance digital circuitry is the speed while in battery driven circuit is power dissipation that ultimately results due to leakage in the circuits. The other reason being the continuous scaling of technology has also resulted in increase of leakage parameters. In this paper, low leakage low power consuming 34 transistor full Subtractor using MTCMOS design technique has been proposed in active and standby mode at different supply voltages. This paper also focused on the minimum voltage that can be used in 43 nm technology using cadence virtuoso tool. Sleep mode leakage current of MTCMOS full subtractor at 0.5V was found to be 4.97 fA and during active mode 1.45 pA. [ABSTRACT FROM AUTHOR]

Estimation of static noise margin (SNM) is believed to be most important step of static random access memory (SRAM) bitcell design. Moreover, the measurement of bitcell stability is a critical issue with scaling of complementary metal-oxide semiconductor (CMOS) technology. Available techniques to find SNM are time consuming and difficult to implement by circuit simulation tool, so there is need of alternate method that can estimate SNM easily. In this article, we present a new method of SNM calculation that is based on curve fitting technique. We calculated SNM of six transistor (6T) SRAM cell with proposed method and established graphical method by varying cell ratio. The correlation coefficient of SNM was 0.99 that indicate proposed technique may be substitution for SNM calculation over conventional graphical method. We believe that we have developed an innovative solution for stability estimation of SRAM bitcell in nanometer technology. [ABSTRACT FROM AUTHOR]