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The relevance of subcortical structures and interhemispheric subcortical-cortical interactions among positive/negative affect and approach/withdrawal tendencies during resting-state are not fully understood. Gaining this knowledge may foster the know-how on their role in subsequent task-engagement and also on the interlinkage among affective measures and approach/withdrawal dichotomy. Here we performed a study based on Region of Interest (ROI)-based analysis and graph-theory estimates for global and subnetworks on a limited sample of healthy 50 male volunteers who recorded resting functional magnetic resonance imaging (fMRI) and self-reported measures of Positive and Negative Affect Schedule (PANAS) and BAS-BIS (Behavioral Activation System-Behavioral Inhibition System) scores. Our study's initial results of region of interest-to-region of interest (ROI-to-ROI) connectivity revealed the connectivity of subcortical neural substrates of PANAS and BAS-BIS scores with bilateralized cortical regions. However, on probing the lateralization of strength of degree measures of the cortical-regions vital for subcortical-cortical interaction, we found, for positive affect, a left-hemispheric proclivity. Further, higher connectivity within the left hemisphere was also observed for the left-lateralized critical cortical regions of negative affect. Our study also revealed the association of emotion and memory-related subcortical-cortical interactions in positive and negative affect. Right amygdala-right thalamus-frontotemporal cortical areas emanated in positive affect, and right putamen-left hippocampus-frontotemporal cortical regions network stemmed for negative affect. Then, we show the involvement of basal-ganglia structures in approach-withdrawal dichotomy with tight coupling of right-caudate, left-accumbens with anterior cingulate, and insular regions for withdrawal/inhibition system. Further, distinct involvement of the insula (posterior) in affective states while insula (anterior) in approach/withdrawal systems builds up for the existence of a feedback loop between affective and approach/withdrawal systems. (PsycInfo Database Record (c) 2021 APA, all rights reserved).

The present investigation is focused on the analog/RF performance of ferroelectric (FE) based substrate metal oxide semiconductor field effect transistor (MOSFET) for digital application as an inverter. Short channel effect (SCEs) reduced significantly with improvement in switching ratio (Ion/Ioff). The simulation shows the immunity towards the parameters like transconductance (gm), transconductance generation factor (TGF), early voltage (VEA) and the intrinsic gain (AV) which allows the device to look into digital application. Also, the RF performance parameters come out to be superior for the proposed device structure, as the gain frequency product (GFP) and gain bandwidth product (GBP) enhanced by 100 and 10 folds, respectively. Further, RF investigation shows the enhanced results as attributed with peak values for transconductance frequency product (TFP) and gain transconductance frequency product (GTFP). The transient analysis shows an improvement in the noise margin (NM) for FE-MOSFET structure. Thus, the proposed architecture can be an attractive alternative for the digital application.

This paper optimizes the fin aspect ratio (AR) of Junctionless Accumulation Mode Gate Stack Gate All Around (JAM-GS-GAA) FinFET with constant conducting channel area for upgraded static, analog, and distortion performance. The crucial static and analog parameters, for instance, electric field, potential, band diagram, electron concentration, transconductance, quality factor, drain current, early voltage, intrinsic gain, output resistance, and output conductance, are evaluated and analyzed. The simulated results reveal that the static and analog performance of JAM-GS-GAA FinFET enhances with the increase in the fin AR. Besides, linearity and distortion parameters like voltage intercept points (VIP2, VIP3), 1-dB compression point, zero crossover point, harmonic distortions (HD2, HD3), and total harmonic distortion are explored. It has been noticed that a low fin AR lessens the distortion in the device and improves the device’s linearity performance. Moreover, the zero crossover point decreased significantly for the device with low fin AR, which reduces the device operation optimum bias point. Thus, the findings of this paper can help engineers to design 3-D devices according to their needs.

In this paper, a novel recessed T-gate double channel HEMT with InGaN back barrier has been designed and studied. The double channel is formed by the AlN layer's insertion below the InAlN/GaN interface, enhancing the drain current density (2.5A/mm). However, double channel HEMT suffers from a lack of gate controllability, due to which device performance decreases. This problem has been resolved by using the InGaN as a back barrier which enhances the carrier confinement of 2DEG by raising the conduction band for the GaN buffer and significantly enhances the gate controllability over a lower channel. Precisely a brief comparison has been done of the proposed device with conventional double channel HEMT. Performance parameters like drain current (Ids), transconductance (gm), intrinsic gain (Av), output conductance (gd), early voltage (VEA), TGF, parasitic capacitances (Cgs, Cgd), cut-off frequency (fT), maximum oscillation frequency (fmax), gain frequency product (GFP), transconductance frequency product (TFP), and gain transconductance frequency product (GTFP) have been investigated. Further, the improvement in linearity parameters such as VIP2, VIP3, IIP3, and 1-dB compression point has been observed by varying the back barrier distance from the lower channel.

Concerned work is solely dedicated to the optimized characteristics of Nanoscale vacuum channel TF (Truncated fin)-FinFET at gate length of 7 nm. NVCTF-FinFET has its own benefit, due to high immune to noise and temperature as compared to TF-FinFET. The working of device stood perfectly well in case of NVCTF-FinFET. When tested, we end up with 3 times less current variation w.r.t temperature, 3 times more efficiency, 104 times more amplifying power analysed at corresponding peak values. These results evident the performance enhancement of NVCTF-FinFET, if seen from analog point of view. When studied from the perspective of linearity for RFIC designs, we end up with enhancement in some figure of merits such as 3.5 times in 1-dB compression point, 4 times more IP3, 102 times in HD3 and around 105 times in IMD3 at corresponding peak values. As NVCTF-FinFET provided descent switching ratio and Vth at input voltage (

In this article, we investigated the impact of temperature variation on DC, analog, RF, and wireless performance of Gate Stack Gate All Around (GS-GAA) FinFET using SILVACO Atlas 3D simulator. The GAA structure introduction enhances the switching ratio (Ion/Ioff) by ∼152.37% and reduces the subthreshold swing (SS) by ∼6.5%. At gate voltage (Vgs) ∼ 0.725 V, the GS-GAA FinFET device exhibits the ZTC (Zero-Temperature-Coefficient) bias point, i.e., the effect of temperature on drain current gets nullified. DC parameters such as leakage current (Ioff), on current (Ion), SS, and threshold voltage (Vth) deteriorate with the rise in temperature. The enhancement in temperature degrades the RF and analog performance of the device by suppressing the parameters like transconductance (gm), device efficiency (TGF), cut-off frequency (fT), gain frequency product (GFP), gain-bandwidth product (GBP), etc. The device’s wireless performance is analyzed using linearity and harmonic distortion parameters such as gm3, gm2, 1-dB compression point, IIP3, VIP3, VIP2, IMD3, HD3, and HD2, and it shows significant improvement as the temperature increases from 300 K to 500 K.

This work presents the analog and RF performance evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET, and the results acquired have been compared with conventional FinFET and GAA FinFET. It has been observed that in comparison to conventional FinFET, leakage current (Ioff) reduces by almost thirty times for the GS-GAA FinFET configuration. Thus, revamping the threshold voltage (Vth), switching ratio (Ion/Ioff), and subthreshold slope (SS) of the proposed device. Also, major analog parameters like transconductance (gm), transconductance generation factor (TGF) enhances considerably with early voltage (VEA) and intrinsic gain (Av) increased by over two times in magnitude for the GS-GAA FinFET configuration. Furthermore, several important RF parameters have been explored, and the outcome of the study is that the GS-GAA FinFET configuration shows superior RF performance. In GS-GAA FinFET configuration, the gain frequency product (GFP) and gain transconductance frequency product (GTFP) amplified by over two times in magnitude with minimal decrease in the cut-off frequency (fT) and maximum oscillation frequency (fmax). Thus, the proposed GS-GAA FinFET device can be looked upon as an appealing option for high-frequency analog/RF applications.

This paper investigates the reliability of a dual metal gate-hetero-material junctionless tunnel FET (DMG-HJLTFET), by using a novel combination of III–V compound semiconducting materials, $$\mathrm{InAs}$$ (lower bandgap) in the source region and $$\mathrm{GaAs}$$ (higher bandgap) in the channel and drain regions. We applied bandgap engineering and dual material gate engineering to improve the linearity metrics and distortion parameters by optimizing an appropriate lower work function tunnel gate toward the source and higher work function supplementary gate toward the drain and compared all the results with SMG (single metal gate)-HJLTFET and Si-JLTFET. The DMG-HJLTFET showed marked improvements in terms of ION, ION/IOFF, SS, $${g}_{\mathrm{m}}$$ , $${g}_{\mathrm{m}3}$$ , VIP2, VIP3, and 1-dB compression point. The input power, IIP3 of DMG-HJLTFET, is 158% greater than SMG-HJLTFET and is 154.7% greater than Si-JLTFET. The distortion power, IMD3 of DMG-HJLTFET, is 171.8% and 20.5% lower than SMG-HJLTFET and Si-JLTFET, respectively, thereby making it suitable for low-power distortion-free wireless communication systems.

Solar energy is quite a reliable and popular source of energy and the recent development in this field has provided a boost for further technological development. Perovskite solar cells (PSCs) research is increasing rapidly due to the fast improvement in their power conversion efficiencies (PCE), easy synthesis as it can be made of common metals, high open-circuit voltage, and cheapness. The presented model is also validated by comparing the obtained values to the existing paper. In this new structure, power conversion efficiency (PCE) is increased from 11.73% to 16.43%. For this purpose, we have used different layers like ITO (Indium Tin Oxide), ZnO (Zinc Oxide) as an electron transporting layer (ETL), CH3NH3PbI3 (Perovskite layer), poly (3,4-ethylene dioxythiophene) (PEDOT) as a Hole transporting layer (HTL) and Gold (Au) as a back contact. We have studied the impact of several factors that may affect the performance and efficiency of solar cells. We have increased efficiency by using ZnO as our Electron transport layer (ETL). The Silvaco Atlas program was used for simulation purposes. Through the device simulation we were able to calculate Current Density (Jsc), Open Circuit Voltage (Voc), Short Circuit Current, Fill Factor and Power. This work will also guide others to further work on the efficiency increment of perovskite solar cells and will also help in the enhancement of efficiencies of low-cost perovskite solar cells.

In this work, we examined the analog and circuitry amplifying capacity of our novel 3 nm Truncated Fin Junctionless bulk FinFET (n-type) with two different oxide thicknesses at this small scale of gate length. Both oxide widths of high K-material HfO2 have their own individual benefits, due to high gate controllability as compared to conventional FinFETs having SiO2 as a gate oxide. The device works best with Tox = 1 nm in terms of power amplification. When tested with this width of gate oxide, we end up with increase of 59.18%, 7.22% and 12.11 times at corresponding peak values of Unilateral power gain (Gu), IP3 and fmax. This actually evident the enhanced performance of TF-FinFET for A.C applications at this high range of frequency of the input signal. When device tested at Tox = 1 nm, we end up with the increase of 45%, 21.45%, 16% and decrease of 65% at the corresponding peak values of Intrinsic delay (ti), Transconductance (gm), Drain current (ID) and OFF-state current (IOFF). These results of simulation also showed the compatibility of TF-FinFET in terms of high-performance analog application. After these analyses, we can expect a strong potential for wide variety of applications to high-speed System on chip from this device.

In this work, the high-temperature reliability of the Black Phosphorus Trench (BP-T) MOSFET device has been analyzed. When the temperature is very high (500 K), the proposed device (BP-T-MOSFET) shows very high reliability with less effects in the device performance. The device is also calibrated with the experimental data. All the simulation has been performed using ATLAS-3D device simulator. BP-T-MOSFET shows high-temperature reliability in terms of reduced sub-threshold current, hot-electron injection gate current, and impact ionization substrate current. Further, higher switching ratio (Ion/Ioff), electron mobility, and electron velocity have also been observed owing to the electrical properties of black phosphorus used in the trench gate which shows the potential in a high-temperature environment. Owing to trench structure and electrical properties of black phosphorus, BP-T-MOSFET has significant device efficiency and low leakage currents at high temperatures which prove as highly shrieked MOS device applications in harsh temperature environment.

Although Tunnel Field Effect Transistors (TFET) offer low leakage current and allow good scalability, but they suffer from low ON-current. Present research paper focuses on the designing of an industry ready TFET that can operate efficiently at nano-scales allowing the fabrication of a smaller and more energy efficient overall device. To achieve the same, the Gate Metal Engineering (GME) and n+ Source Pocket (SP) schemes have been integrated on Double-Gate TFET (DG-TFET). For a distinct examination of the merits of GME and SP, 4 types of TFET architectures, namely the DG-TFET, GME-DG-TFET, SP-DG-TFET and GME-SP-DG-TFET (which amalgamates the merits of both GME and SP engineering) are investigated. All these device architectures are examined in terms of their electrical characteristics and analog parameters. GME-SP-DG-TFET (being superior among the four) is further analyzed under the presence of interface fixed charges (FC) of different polarity to affirm its reliability. Investigations of this device structure reveal that the positive FC are more noxious for the device as compared to negative FC. However, the enhanced flatband voltage under the negative FC translates to the high gate bias requirement to turn the device ON. Observance of only marginal variations in the parasitic capacitances and efficiency of the GME-SP-DG-TFET device in the presence of FC (both positive/negative) signifies its immunity and promises enhanced reliability. A remarkable improvement of the ION/IOFF by two order of magnitude (from 1010 to 1012) and a decrease in Vth by 27.71% observed for GME-SP-DG-TFET as compared to DG-TFET along with the improved reliability makes the former an efficient candidate for low power analog/RF applications.