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179 results on '"Rochange, Christine"'

1. EMSBench: Benchmark and Testbed for Reactive Real-Time Systems

Author

Kluge, Florian, Rochange, Christine, and Ungerer, Theo

Subjects
real-time benchmark, wcet analysis, engine management system, Technology, Electrical engineering. Electronics. Nuclear engineering, TK1-9971, Electronics, TK7800-8360
Abstract

Benchmark suites for real-time embedded systems (RTES) usually contain only pure computations that are often used in this domain. They allow to evaluate computing performance, but do not reproduce the complexity and behaviour that is typical for such systems. Actual RTES have to interact with the physical environment, which is often reflected by code that is executed concurrently. In this article, we present the software package EMSBench that mimics such complex behaviour, and highlight some of its use cases. The benchmark code ems of EMSBench is based on the open-source engine management system (EMS) FreeEMS. Additionally, EMSBench contains a trace generator (tg) that provides input signals for ems and enables to execute ems close to reality. We provide detailed descriptions of the ems's execution behaviour and of trace generation. EMSBench can be used as test or benchmark program to compare different hardware platforms, e.g. in terms of schedulability. Also, we use EMSBench as a benchmark for static worst-case execution time (WCET) analysis and compare these results to measurements performed on existing hardware. Our results based on the OTAWA WCET estimation tool show WCET overestimations by the static analysis from 11.9% to 41.1% depending on the complexity of the analysed functions.

Published
2017
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2. Computing Execution Times with eXecution Decision Diagrams in the Presence of Out-Of-Order Resources

Author

Bai, Zhenyu, Cassé, Hugues, Carle, Thomas, and Rochange, Christine

Subjects
Electrical Engineering and Systems Science - Systems and Control, Computer Science - Hardware Architecture
Abstract

Worst-Case Execution Time (WCET) is a key component for the verification of critical real-time applications. Yet, even the simplest microprocessors implement pipelines with concurrently-accessed resources, such as the memory bus shared by fetch and memory stages. Although their in-order pipelines are, by nature, very deterministic, the bus can cause out-of-order accesses to the memory and, therefore, timing anomalies: local timing effects that can have global effects but that cannot be easily composed to estimate the global WCET. To cope with this situation, WCET analyses have to generate important over-estimations in order to preserve safety of the computed times or have to explicitly track all possible executions. In the latter case, the presence of out-of-order behavior leads to a combinatorial blowup of the number of pipeline states for which efficient state abstractions are difficult to design. This paper proposes instead a compact and exact representation of the timings in the pipeline, using eXecution Decision Diagram (XDD) [1]. We show how XDD can be used to model pipeline states all along the execution paths by leveraging the algebraic properties of XDD. This computational model allows to compute the exact temporal behavior at control flow graph level and is amenable to efficiently and precisely support WCET calculation in presence of out-of-order bus accesses. This model is finally experimented on the TACLe benchmark suite and we observe good performance making this approach appropriate for industrial applications.

Published
2022

3. A framework to experiment optimizations for real-time and embedded software

Author

Cassé, Hugues, Heydemann, Karine, Ozaktas, Haluk, Ponroy, Jonathan, Rochange, Christine, and Zendra, Olivier

Subjects
Computer Science - Performance
Abstract

Typical constraints on embedded systems include code size limits, upper bounds on energy consumption and hard or soft deadlines. To meet these requirements, it may be necessary to improve the software by applying various kinds of transformations like compiler optimizations, specific mapping of code and data in the available memories, code compression, etc. However, a transformation that aims at improving the software with respect to a given criterion might engender side effects on other criteria and these effects must be carefully analyzed. For this purpose, we have developed a common framework that makes it possible to experiment various code transfor-mations and to evaluate their impact of various criteria. This work has been carried out within the French ANR MORE project., Comment: International Conference on Embedded Real Time Software and Systems (ERTS2), Toulouse : France (2010)

Published
2010

5. Warp-Level CFG Construction for GPU Kernel WCET Analysis

Author

Louison Jeanmougin and Pascal Sotin and Christine Rochange and Thomas Carle, Jeanmougin, Louison, Sotin, Pascal, Rochange, Christine, Carle, Thomas, Louison Jeanmougin and Pascal Sotin and Christine Rochange and Thomas Carle, Jeanmougin, Louison, Sotin, Pascal, Rochange, Christine, and Carle, Thomas

Abstract

We present an abstract interpretation technique to automatically build a Control Flow Graph (CFG) representation of the execution of a GPU kernel. GPUs implement an inherently parallel execution model, in which threads are grouped within so-called warps that execute in lockstep. This execution model enables the representation of the execution of the threads of a warp as a single CFG. However, thread divergence may appear within a warp and its effect must be captured explicitly within the CFG. Our method builds the CFG of a warp by applying abstract interpretation on the assembly (Nvidia SASS) code of a kernel, and by maintaining an abstract representation of which threads within the warp agree on which values. This allows the method to detect precisely the points in the program where thread divergence may occur, and avoid spurious reactivation edges in the CFG. We apply our technique on benchmark kernels as a proof-of-concept, and generate IPET systems using the resulting CFGs.

Published
2023
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6. Validation of Processor Timing Models Using Cycle-Accurate Timing Simulators

Author

Alban Gruin and Thomas Carle and Christine Rochange and Pascal Sainrat, Gruin, Alban, Carle, Thomas, Rochange, Christine, Sainrat, Pascal, Alban Gruin and Thomas Carle and Christine Rochange and Pascal Sainrat, Gruin, Alban, Carle, Thomas, Rochange, Christine, and Sainrat, Pascal

Abstract

We propose a workflow to help find errors in the processor models that are used to prove their timing predictability. Recently, several papers have modeled processor cores using formal models that represent how instructions progress through the pipeline in each execution cycle. However, such models grow with the complexity of the cores and they are built by hand, using a description of the core, usually the HDL-level code. Such a task is error-prone, and verifying that the model actually captures the core’s timing behavior is required, otherwise the proofs become useless. Our workflow simulates the execution of benchmark applications using the HDL specification of a core in order to extract timing information as well as other relevant information (e.g. cache miss events, branch mispredictions). This information is used to replay the execution in a simulator of the core timing model, and to determine whether or not the model accurately represents the execution timing of the instructions. To avoid writing the simulator by hand for each new core, or new variation of a core, we developed a compiler that translates the timing model of a core into a C++ program. We evaluated our approach on the open source MINOTAuR core and we show how it enabled us to detect and correct errors in its model.

Published
2023
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8. Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets

Author

Bourgade, Roman, Rochange, Christine, Sainrat, Pascal, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Kubátová, Hana, editor, Hochberger, Christian, editor, Daněk, Martin, editor, and Sick, Bernhard, editor

Published
2013
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10. OTAWA: An Open Toolbox for Adaptive WCET Analysis

Author

Ballabriga, Clément, Cassé, Hugues, Rochange, Christine, Sainrat, Pascal, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Min, Sang Lyul, editor, Pettit, Robert, editor, Puschner, Peter, editor, and Ungerer, Theo, editor

Published
2010
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11. A Context-Parameterized Model for Static Analysis of Execution Times

Author

Rochange, Christine, Sainrat, Pascal, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, and Stenström, Per, editor

Published
2009
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12. A Predictable Simultaneous Multithreading Scheme for Hard Real-Time

Author

Barre, Jonathan, Rochange, Christine, Sainrat, Pascal, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Brinkschulte, Uwe, editor, Ungerer, Theo, editor, Hochberger, Christian, editor, and Spallek, Rainer G., editor

Published
2008
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14. PasTiS: building an NVIDIA Pascal GPU simulator for embedded AI applications

Author

Adalbert, Michaël, Carle, Thomas, Rochange, Christine, and ROCHANGE, Christine

Subjects
cycle-accurate simulator, timing analysis, GPU, [INFO] Computer Science [cs]
Abstract

We present PasTiS, a simulator for the NVIDIA Pascal GPU architecture family, with a focus on timing simulation. PasTiS supports a subset of the Pascal ISA, sufficient to simulate the execution of neural networks. We present this subset, as well as the underlying microarchitecture that we modelled using information available from NVIDIA, from scientific publications, and from our own experiments. We demonstrate the precision of the simulator by comparing it to measurements on the NVIDIA Jetson TX2 development board, on neural network applications.

Published
2022

22. Multicores

Author

Rochange, Christine, primary, Uhrig, Sascha, additional, and Sainrat, Pascal, additional

Published
2014
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29. A Framework for CalculatingWCET Based on Execution Decision Diagrams.

Author

BAI, ZHENYU, CASSÉ, HUGUES, MICHIEL, MARIANNE DE, CARLE, THOMAS, and ROCHANGE, CHRISTINE

Subjects
MODERN architecture, LINEAR programming, DATA structures, LINEAR systems, DECISION making, INTEGER programming, AD hoc computer networks
Abstract

Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-case Execution Time (WCET) analysis methods tend to scale poorly to modern hardware architectures. As a result, a trade-off must be found between the duration and the precision of the analysis, leading to an overestimation of the WCET bounds. In turn, this reduces the schedulability and resource usage of the system. In this article,we present a new data structure to speed up the analysis: the eXecution Decision Diagram (XDD), which is an ad hoc extension of Binary Decision Diagrams tailored for WCET analysis problems. We show how XDDs can be used to represent efficiently execution states in a modern hardware platform. Moreover, we propose a new process to build the Integer Linear Programming system of the Implicit Path Enumeration Technique using XDD. We use benchmark applications to demonstrate how the use of an XDD substantially increases the scalability of WCET analysis and the precision of the obtained WCET. [ABSTRACT FROM AUTHOR]

Published
2022
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31. TACLeBench : a benchmark collection to support worst-case execution time research

Author

Falk, Heiko, Altmeyer, Sebastian, Hellinckx, Peter, Lisper, Björn, Puffitsch, Wolfgang, Rochange, Christine, Schoeberl, Martin, Sørensen, Rasmus Bo, Wägemann, Peter, Wegener, Simon, Falk, Heiko, Altmeyer, Sebastian, Hellinckx, Peter, Lisper, Björn, Puffitsch, Wolfgang, Rochange, Christine, Schoeberl, Martin, Sørensen, Rasmus Bo, Wägemann, Peter, and Wegener, Simon

Abstract

Engineering related research, such as research on worst-case execution time, uses experimentation to evaluate ideas. For these experiments we need example programs. Furthermore, to make the research experimentation repeatable those programs shall be made publicly available. We collected open-source programs, adapted them to a common coding style, and provide the collection in open-source. The benchmark collection is called TACLeBench and is available from GitHub in version 1.9 at the publication date of this paper. One of the main features of TACLeBench is that all programs are self-contained without any dependencies on standard libraries or an operating system.

Published
2020

32. Using execution graphs to model a prefetch and write buffers and its application to the Bostan MPPA

Author

Sun, Wei-Tsun, Cassé, Hugues, Rochange, Christine, Rihani, Hamza, Maiza, Claire, SUN, Wei-Tsun, Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), VERIMAG (VERIMAG - IMAG), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
pipeline analysis, static analysis, VLIW, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, Real-Time, WCET, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems
Abstract

International audience; Verifying the temporal properties of critical systems embedded in vehicles, like planes or cars, is crucial to avoid catastrophic issues. A key component of this verification is the Worst Case Execution Time (WCET) of the programs composing these systems. A common and sound approach to compute WCET is based on static analysis of the programs that requires, in turn, to precisely model the behavior and the timings of the hardware. Processor-specific features such as pipelines, caches, and buffers influence the hardware performances significantly. Hence taking processor features into account when estimating WCET is essential. Modeling the processor's features formally to ensure safe and accurate estimation is then a must. In this paper, we present the methodology applied to capture the behavior of prefetch and write buffers of the Kalray Bostan MPPA microprocessor, and to incorporate the established models with the Execution Graph (XG) to obtain WCET estimation. These analyses are then applied to the Mälardalen benchmark suite and the experimentation results validate the feasibility of our approach.

Published
2018

33. The W-SEPT Project: Towards Semantic-Aware WCET Estimation

Author

Maiza, Claire, Raymond, Pascal, Parent-Vigouroux, Catherine, Bonenfant, Armelle, Carrier, Fabienne, Cassé, Hugues, Cuenot, Philippe, Claraz, Denis, Halbwachs, Nicolas, Jahier, Erwan, Li, Hanbing, de Michiel, Marianne, Mussot, Vincent, Puaut, Isabelle, Rochange, Christine, Rohou, Erven, Ruiz, Jordy, Sotin, Pascal, Sun, Wei-Tsun, VERIMAG (VERIMAG - IMAG), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Continental Automotive France [Toulouse], Pushing Architecture and Compilation for Application Performance (PACAP), Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-ARCHITECTURE (IRISA-D3), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-CentraleSupélec-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), ARCHITECTURE (IRISA-D3), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), ANR-12-INSE-0001,W-SEPT,WCET: SEmantique, Précision, Traçabilité(2012), Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes 1 (UR1), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Toulouse Mind & Brain Institut (TMBI), Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], 000 Computer science, knowledge, general works, Computer Science, 0202 electrical engineering, electronic engineering, information engineering, Program analysis, 020207 software engineering, 02 engineering and technology, Worst-case execution time analysis, Static analysis
Abstract

International audience; Critical embedded systems are generally composed of repetitive tasks that must meet hard timing constraints, such as termination deadlines. Providing an upper bound of the worst-case execution time (WCET) of such tasks at design time is necessary to guarantee the correctness of the system. In static WCET analysis, a main source of over-approximation comes from the complexity of the modern hardware platforms: their timing behavior tends to become more unpredictable because of features like caches, pipeline, branch prediction, etc. Another source of over-approximation comes from the software itself: WCET analysis may consider potential worst-cases executions that are actually infeasible, because of the semantics of the program or because they correspond to unrealistic inputs. The W-SEPT project, for “WCET, Semantics, Precision and Traceability”, has been carried out to study and exploit the influence of program semantics on the WCET estimation. This paper presents the results of this project : a semantic-aware WCET estimation workflow for high-level designed systems.

Published
2017
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34. A Parallelization Approach for Hard Real-Time Systems and Its Application on Two Industrial Programs

Author

Rochange, Christine, Frieb, Martin, Jahr, Ralf, Ozaktas, Haluk, Hugl, Andreas, Regler, Hans, Ungerer, Theo, Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, University of Augsburg [Augsburg], Bauer Group (GERMANY), Institute of Computer Science - University of Augsburg (ICS), and Universität Augsburg [Augsburg]

Subjects
[INFO]Computer Science [cs]
Abstract

International audience; Applications in industry often have grown and improved over many years. Since their performance demands increase, they also need to benefit from the availability of multi-core processors. However, a reimplementation from scratch and even a restructuring of these industrial applications is very expensive, often due to high certification efforts. Therefore, a strategy for a systematic parallelization of legacy code is needed. We present a parallelization approach for hard real-time systems, which ensures a high reusage of legacy code and preserves timing analysability. To show its applicability, we apply it on the core algorithm of an avionics application as well as on the control program of a large construction machine. We create models of the legacy programs showing the potential of parallelism, optimize them and change the source codes accordingly. The parallelized applications are placed on a predictable multi-core processor with up to 18 cores. For evaluation, we compare the worst case execution times and their speedups. Furthermore, we analyse limitations coming up at the parallelization process.

Published
2016
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35. Multiplexing Adaptive with Classic AUTOSAR? Adaptive Software Control to Increase Resource Utilization in Mixed-Critical Systems

Author

Kritikakou, Angeliki, Marty, Thibaut, Pagetti, Claire, Rochange, Christine, Lauer, Michael, Roy, Matthieu, Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN), Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-ARCHITECTURE (IRISA-D3), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), ONERA - The French Aerospace Lab [Toulouse], ONERA, Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Toulouse Mind & Brain Institut (TMBI), Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Équipe Tolérance aux fautes et Sûreté de Fonctionnement informatique (LAAS-TSF), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), CentraleSupélec-Télécom Bretagne-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Télécom Bretagne-Université de Rennes 1 (UR1), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-École normale supérieure - Rennes (ENS Rennes)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Centre National de la Recherche Scientifique - CNRS (FRANCE), Institut National Polytechnique de Toulouse - INPT (FRANCE), Institut National de la Recherche en Informatique et en Automatique - INRIA (FRANCE), Institut National des Sciences Appliquées de Rennes - INSA (FRANCE), Institut Mines-Télécom (FRANCE), Office National d'Etudes et Recherches Aérospatiales - ONERA (FRANCE), Ecole Supérieure d'Electricité - SUPELEC (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Université de Bretagne Sud - UBS (FRANCE), Université de Rennes 1 (FRANCE), Institut de Recherche en Informatique de Toulouse - IRIT (Toulouse, France), and Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE)

Subjects
Resources Utilization, Architectures Matérielles, Système d'exploitation, Réseaux et télécommunications, Safety, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], Dynamic management, Systèmes embarqués, Real-time systems, Multi/Many-core systems, Run-time monitoring
Abstract

International audience; Automotive embedded systems need to cope with antagonist requirements: on the one hand, the users and market pressure push car manufacturers to integrate more and more services that go far beyond the control of the car itself. On the other hand, recent standardization efforts in the safety domain has led to the development of the ISO 26262 norm that defines means and requirements to ensure the safe operation of automotive embedded systems. In particular, it led to the definition of ASIL (Automotive Safety and Integrity Levels), i.e., it formally defines several criticality levels. Handling the increased complexity of new services makes new architectures, such as multi or many-cores, appealing choices for the car industry. Yet, these architectures provide a very low level of timing predictability due to shared resources, which goes in contradiction with timing guarantees required by ISO 26262. For highest criticality level tasks, Worst-Case Execution Time analysis (WCET) is required to guarantee that timing constraints are respected. The WCET analyzers consider the worst-case scenario: whenever a critical task accesses a shared resource in a multi/many-core platform, a WCET analyzer considers that all cores use the same resource concurrently. To improve the system performance, we proposed in a earlier work an approach where a critical task can be run in parallel with less critical tasks, as long as the real-time constraints are met. When no further interferences can be tolerated, the proposed run-time control suspends the low critical tasks until the termination of the critical task. In an automotive context, the approach can be translated as a highly critical partition, namely a classic AUTOSAR one, that runs on one dedicated core, with several cores running less critical Adaptive AUTOSAR application(s). We briefly describe the design of our proven-correct approach. Our strategy is based on a graph grammar to formally model the critical task as a set of control flow graphs on which a safe partial WCET analysis is applied and used at run-time to control the safe execution of the critical task.

Published
2016

36. TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research

Author

Falk, Heiko, Altmeyer, Sebastian, Hellinckx, Peter, Lisper, Björn, Puffitsch, Wolfgang, Rochange, Christine, Schoeberl, Martin, Sørensen, Rasmus Bo, Wägemann, Peter, Wegener, Simon, Hamburg University of Technology (TUHH), University of Luxembourg [Luxembourg], Universiteit Antwerpen [Antwerpen], Mälardalen University (MDH), Institute of Computer Engineering [Vienna], Vienna University of Technology (TU Wien), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Technical University of Denmark [Lyngby] (DTU), Friedrich-Alexander Universität Erlangen-Nürnberg (FAU), AbsInt GmbH (Angewandte Informatik), and AbsInt

Subjects
Interactive computer systems, 000 Computer science, knowledge, general works, Geography, Planning and Development, WCET analysis, Real time systems, 02 engineering and technology, Informatik [004], Benchmark, 020202 computer hardware & architecture, Worst-case execution time, Benchmarking, benchmark, real-time systems, Modeling and Simulation, Computer Science, 0202 electrical engineering, electronic engineering, information engineering, 004: Informatik, [INFO]Computer Science [cs], 020201 artificial intelligence & image processing, Standard libraries, Open source projects, ddc:004, Open sources, Engineering sciences. Technology, Real-time systems
Abstract

International audience; Engineering related research, such as research on worst-case execution time, uses experimentation to evaluate ideas. For these experiments we need example programs. Furthermore, to make the research experimentation repeatable those programs shall be made publicly available. We collected open-source programs, adapted them to a common coding style, and provide the collection in open-source. The benchmark collection is called TACLeBench and is available from GitHub in version 1.9 at the publication date of this paper. One of the main features of TACLeBench is that all programs are self-contained without any dependencies on standard libraries or an operating system. 1998 ACM Subject Classification C.3 [Special-Purpose and Application-Based Systems] Real-Time and Embedded Systems

Published
2016
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37. Parallel Real-Time Tasks, as viewed by WCET Analysis and Task Scheduling Approaches

Author

Rochange, Christine, Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE), Centre National de la Recherche Scientifique - CNRS (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, and Institut National Polytechnique de Toulouse - INPT (FRANCE)

Subjects
000 Computer science, knowledge, general works, Architectures Matérielles, Multicore, Worst-case response time analysis, Computer Science, Schedulability, Système d'exploitation, Réseaux et télécommunications, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, Parallel tasks, Worst-case execution time analysis, Systèmes embarqués
Abstract

International audience; With the advent of multi-core platforms, research in the field of hard real-time has recently considered parallel software, from the perspective of both worst-case execution time (WCET) and task schedulability (or worst-case response time, WCRT) analyses. These two areas consider task models that are not completely identical and sometimes make different assumptions. This paper draws a brief overview of the state of the art in the timing analysis of parallel tasks and tries to identify points of convergence and divergence between the existing approaches.

Published
2016

38. Case study: Performance and WCET analysis for parallelised avionic applications with ODC2

Author

Pyka, Arthur, Zaykov, Pavel G., Cassé, Hugues, Ozaktas, Haluk, Rochange, Christine, Uhrig, Sascha, Technische Universität Dortmund [Dortmund] (TU), Honeywell International S.r.o. [Prague], Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), IEEE Industrial Electronics Society, and Anglia Ruskin University

Subjects
Multicore processing, Hardware_MEMORYSTRUCTURES, Three-dimensional displays, Aerospace electronics, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, Synchronization, Coherence
Abstract

International audience; In a hard Real-Time (HRT) domain such as avionics, the high application performance is as important as delivering a predictable execution time. More precisely, the performance is defined by the application Worst-Case Execution Time (WCET). A common practice to boost the application performance in general purpose computing is by parallelisation and parallel execution on a shared memory multicore processor. Hence, local caches, used for bridging the long memory latency, need to allow coherent accesses to shared data. Conventional cache coherence protocols impede a suitable timing analysis because of multiple reasons. In this paper, we introduce an avionics case study to analyse the applicability of the earlier proposed On-Demand Coherent Cache (ODC 2 ). We experiment with a 3D Path Planning (3DPP) application executed on a multicore processor. By varying the number of cores and the level of application parallelism, we compare and analyse observed average case execution times (ACET) of the 3DPP application with ODC 2 , Uncached (bypassing the cache for shared data), and Cache Flush (software-triggered cache invalidation) configurations. The ACET results of the 3DPP application suggest that ODC 2 significantly outperforms the Uncached configuration by 1.53 times and Cache Flush by 2.15 times. Furthermore, we study the WCET speedup of the 3DPP application by applying a static analysis OTAWA tool. In terms of worst-case performance, the ODC 2 achieves a speedup of 1.63 compared to Uncached and 3.17 compared to Cache Flush configurations.

Published
2015
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39. WCET and Mixed-criticality: How to Quantify the Confidence in WCET Estimations?

Author

Altmeyer, Sebastian, Lisper, Björn, Maiza, Claire, Reineke, Jan, Rochange, Christine, University of Luxemburg, Mälardalen University (MDH), VERIMAG (VERIMAG - IMAG), Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique de Grenoble (INPG)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Joseph Fourier - Grenoble 1 (UJF), Compiler Design Lab [Saarbrücken], Saarland University [Saarbrücken], Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
confidence in WCET estimates, WCET analysis, [INFO]Computer Science [cs], mixed criticality
Abstract

International audience; Mixed-criticality systems integrate components of different criticality. Different criticality levels require different levels of confidence in the correct behavior of a component. One aspect of correctness is timing. Confidence in worst-case execution time (WCET) estimates depends on the process by which they have been obtained. A somewhat naive view is that static WCET analyses determines safe bounds in which we can have absolute confidence, while measurement-based approaches are inherently unreliable. In this paper, we refine this view by exploring sources of doubt in the correctness of both static and measurement-based WCET analysis.

Published
2015
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40. EMSBench: Benchmark and Testbed for Reactive Real-Time Systems

Author

Florian Kluge and Christine Rochange and Theo Ungerer, Kluge, Florian, Rochange, Christine, Ungerer, Theo, Florian Kluge and Christine Rochange and Theo Ungerer, Kluge, Florian, Rochange, Christine, and Ungerer, Theo

Abstract

Benchmark suites for real-time embedded systems (RTES) usually contain only pure computations that are often used in this domain. They allow to evaluate computing performance, but do not reproduce the complexity and behaviour that is typical for such systems. Actual RTES have to interact with the physical environment, which is often reflected by code that is executed concurrently. In this article, we present the software package EMSBench that mimics such complex behaviour, and highlight some of its use cases. The benchmark code ems of EMSBench is based on the open-source engine management system (EMS) FreeEMS. Additionally, EMSBench contains a trace generator (tg) that provides input signals for ems and enables to execute ems close to reality. We provide detailed descriptions of the ems's execution behaviour and of trace generation. EMSBench can be used as test or benchmark program to compare different hardware platforms, e.g. in terms of schedulability. Also, we use EMSBench as a benchmark for static worst-case execution time (WCET) analysis and compare these results to measurements performed on existing hardware. Our results based on the OTAWA WCET estimation tool show WCET overestimations by the static analysis from 11.9% to 41.1% depending on the complexity of the analysed functions.

Published
2017
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41. WCET Analysis of Parallel Benchmarks using On-Demand Coherent Cache

Author

Pyka, Arthur, Tadros, Lillian, Uhrig, Sascha, Cassé, Hugues, Ozaktas, Haluk, Rochange, Christine, Technische Universität Dortmund [Dortmund] (TU), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), and Grélaud, Françoise

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs], ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2015

42. Experiences and Results of Parallelisation of Industrial Hard Real-time Applications for the parMERASA Multi-core

Author

Ungerer, Theo, Bradatsch, Christian, Frieb, Martin, Kluge, Florian, Mische, Jörg, Stegmeier, Alexander, Jahr, Ralf, Gerdes, Mike, Zaykov, Pavel, Matusova, Lucie, Li, Zai Jian Jia, Petrov, Zlatko, Böddeker, Bert, Kehr, Sebastian, Regler, Hans, Hugl, Andreas, Rochange, Christine, Ozaktas, Haluk, Cassé, Hugues, Bonenfant, Armelle, Sainrat, Pascal, Lay, Nick, George, David, Broster, Ian, Quinones, Eduardo, Panic, Milos, Abella, Jaume, Hernandez, Carles, Cazorla, Francisco, Uhrig, Sascha, Rohde, Mathias, Pyka, Arthur, University of Augsburg (UNIA), Institute of Computer Science - University of Augsburg (ICS), Universität Augsburg [Augsburg], Honeywell International S.r.o. [Prague], DENSO AUTOMOTIVE Deutschland, Bauer Group (GERMANY), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Toulouse Mind & Brain Institut (TMBI), Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Université Toulouse III - Paul Sabatier (UT3), Rapita Systems Ltd [York], Rapida Systems, Barcelona Supercomputing Center - Centro Nacional de Supercomputacion (BSC - CNS), Technische Universität Dortmund [Dortmund] (TU), Luís Miguel Pinho, CISTER, Portugal, Eduardo Quiñones, BSC, Spain, Sascha Uhrig, TU Dortmund, Germany, HiPEAC : European Network on High-performance Embedded Architecture and Compilation, European Project: 287519, Grélaud, Françoise, European Union Seventh Framework Programme - 287519 - INCOMING, University of Augsburg [Augsburg], Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs]
Abstract

International audience; The EC FP-7 project parMERASA (Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability, Oct. 1, 2011 until Sept. 30, 2014) provides a timing analysable system of parallel hard real-time applications running on a scalable multi-core processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelising hard real-time programs to run on predictable multi-/many-core processors. A software engineering approach was developed to ease sequential to parallel program transformation by developing and supporting suitable parallel design patterns that are analysable. The following sequential hard real-time programs were parallelised by applying the pattern-oriented parallelisation approach: 3D path planning and stereo navigation algorithms (Honeywell International s.r.o.), diesel engine management system (DENSO AUTOMOTIVE Deutschland GmbH), and the control algorithm for a dynamic compaction machine (BAUER Maschinen GmbH). The paper reports on parallelisation approach, experiences made during parallelisation with applications, tools and multi-core architecture, scalability of applications and quantitative results reached.

Published
2015

43. A Framework to Quantify the Overestimations of Static WCET Analysis

Author

Cassé, Hugues, Ozaktas, Haluk, Rochange, Christine, Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), Institut National Polytechnique de Toulouse - INPT (FRANCE), Centre National de la Recherche Scientifique - CNRS (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), and Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], 000 Computer science, knowledge, general works, Système d'exploitation, Uncertainty, Réseaux et télécommunications, Static WCET analysis, ComputerApplications_COMPUTERSINOTHERSYSTEMS, Systèmes embarqués, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], Architectures Matérielles, Cache analysis, Computer Science, Overestimation, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, ComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMS, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS]
Abstract

International audience; To reduce complexity while computing an upper bound on the worst-case execution time, static WCET analysis performs over-approximations. This feeds the general feeling that static WCET estimations can be far above the real WCET. This feeling is strengthened when these estimations are compared to measured execution times: generally, it is very unlikely to capture the worstcase from observations, then the difference between the highest watermark and the proven WCET upper bound might be considerable. In this paper, we introduce a framework to quantify the possible overestimation on WCET upper bounds obtained by static analysis. The objective is to derive a lower bound on the WCET to complement the upper bound.

Published
2015
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44. The International Journal of Time-Critical Computing Systems - Special Issue: Optimization of Real-Time Systems (2014)

Author

Anderson, James Hampton, Rochange, Christine, University of North Carolina [Chapel Hill] (UNC), University of North Carolina System (UNC), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
[INFO]Computer Science [cs]
Abstract

International audience; In many application domains, such as automotive, avionics, telecommunications, process control or multimedia, software components must fulfill timing constraints. In such real-time systems, the timely delivery of results is as important as their correctness. Guaranteeing that tasks can meet their deadlines requires using specific design and analysis techniques that include task and message scheduling considering various kinds of supporting platforms, model-driven development, worst-case execution time estimation, design of time-predictable infrastructures, real-time-specific compilers, programming languages, middleware and operating systems. These topics are at the heart of several annual international conferences that gather researchers from all around the world. The real-time and network systems conference (RTNS) is one of them. This special issue focuses on the optimization of real-time systems. It includes extended versions of three selected papers that have been presented at the 20th RTNS held in Pont-à-Mousson, France, in November 2012. Each paper includes significant extra material and has been peer-reviewed to meet the quality standard required by the journal.

Published
2014

45. Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore

Author

Ungerer, Theo, primary, Bradatsch, Christian, additional, Frieb, Martin, additional, Kluge, Florian, additional, Mische, Jörg, additional, Stegmeier, Alexander, additional, Jahr, Ralf, additional, Gerdes, Mike, additional, Zaykov, Pavel, additional, Matusova, Lucie, additional, Li, Zai Jian Jia, additional, Petrov, Zlatko, additional, Böddeker, Bert, additional, Kehr, Sebastian, additional, Regler, Hans, additional, Hugl, Andreas, additional, Rochange, Christine, additional, Ozaktas, Haluk, additional, Cassé, Hugues, additional, Bonenfant, Armelle, additional, Sainrat, Pascal, additional, Lay, Nick, additional, George, David, additional, Broster, Ian, additional, Quiñones, Eduardo, additional, Panic, Milos, additional, Abella, Jaume, additional, Hernandez, Carles, additional, Cazorla, Francisco, additional, Uhrig, Sascha, additional, Rohde, Mathias, additional, and Pyka, Arthur, additional

Published
2016
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46. Estimation de temps d'exécution et délais

Author

Maïza, Claire, Raymond, Pascal, Rochange, Christine, Grélaud, Françoise, Chetto, Maryline, VERIMAG (VERIMAG - IMAG), Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique de Grenoble (INPG)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Joseph Fourier - Grenoble 1 (UJF), Institut national de recherches archéologiques préventives (Inrap), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs]
Abstract

ISBN ebook : 9781784060398; International audience

Published
2014

47. Contention in multicore hardware shared resources: Understanding of the state of the art

Author

Fernández, Gabriel, Abella Ferrer, Jaume, Quiñones, Eduardo, Rochange, Christine, Vardanega, Tullio, Cazorla Almeida, Francisco Javier, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center – Centro Nacional de Supercomputación - BSC-CNS (SPAIN), Centre National de la Recherche Scientifique - CNRS (FRANCE), Consejo Superior de Investigaciones Científicas - CSIC (SPAIN), Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Universitat Politècnica de Catalunya - UPC (SPAIN), Università degli Studi di Padova (ITALY), and Institut de Recherche en Informatique de Toulouse - IRIT (Toulouse, France)

Subjects
000 Computer science, knowledge, general works, Architectures Matérielles, Computer Science, Système d'exploitation, WCET analysis, Réseaux et télécommunications, Real-time data processing, Contention, Multicores, Systèmes embarqués, Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC], Temps real (Informàtica)
Abstract

The real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been accentuated with the arrival of multicore processors. From the state of the art on the subject, there appears to be considerable diversity in the understanding of the problem and in the “approach” to solve it. This sparseness makes it difficult for any reader to form a coherent picture of the problem and solution space. This paper draws a tentative taxonomy in which each known approach to the problem can be categorised based on its specific goals and assumptions.

Published
2014

48. Worst-Case Communication Overhead in a Many-Core based Shared-Memory Model

Author

Dkhil, Amira, Louise, Stéphane, Rochange, Christine, Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Commissariat à l'Energie Atomique et aux énergies alternatives - CEA (FRANCE), Centre National de la Recherche Scientifique - CNRS (FRANCE), Institut National Polytechnique de Toulouse - INPT (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Toulouse Mind & Brain Institut (TMBI), Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), and Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Hardware_MEMORYSTRUCTURES, Système d'exploitation, Réseaux et télécommunications, CSDF, Systèmes embarqués, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], Architectures Matérielles, Shared memor, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, MPPA chip, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS], Multi-core, Access time
Abstract

National audience; With emerging many-core architectures, using on-chip shared memories is an interesting approach because it provides high bandwidth and high throughput data exchange. Such a feature is usually implemented as a multi-bus multi-banked memory. Since predicting timing behavior is key to efficient design and verification of embedded real-time systems, the question that arises is how to evaluate the access time for one memory access of a given task while others may concurrently access the same memory-bank at t the same time. In this paper, we give the answers for a subset of streaming applications modeled like CSDF Model of Computation and implemented in Kalray’s MPPA chip.

Published
2013

49. Monitoring On-line Timing Information to Support Mixed-Critical Workloads

Author

Kritikakou, Angeliki, Baldellon, Olivier, Pagetti, Claire, Rochange, Christine, Roy, Matthieu, Vargas, Fabian, Centre National de la Recherche Scientifique - CNRS (FRANCE), Institut National Polytechnique de Toulouse - INPT (FRANCE), Institut National des Sciences Appliquées de Toulouse - INSA (FRANCE), Institut Supérieur de l'Aéronautique et de l'Espace - ISAE-SUPAERO (FRANCE), Office National d'Etudes et Recherches Aérospatiales - ONERA (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Pontificia Universidade Catolica do Rio Grande do Sul - PUCRS (BRAZIL), Laboratoire d'Analyse et d'Architecture des Systèmes - LAAS (Toulouse, France), ONERA - The French Aerospace Lab [Toulouse], ONERA, Équipe Tolérance aux fautes et Sûreté de Fonctionnement informatique (LAAS-TSF), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Toulouse Mind & Brain Institut (TMBI), Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Pontifical Catholic University of Rio Grande do Sul (PUC-RS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Pontifícia Universidade Católica do Rio Grande do Sul [Porto Alegre] (PUCRS), and Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE)

Subjects
Mixed-critical workloads, Architectures Matérielles, Worst case execution time, Système d'exploitation, Réseaux et télécommunications, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], Systèmes embarqués
Abstract

International audience; Many/multi-cores architectures provide tremendous increase in computation power, increasing the possibility of executing additional tasks on the system. In critical embedded systems, e.g. aeronautical systems, the uncertainty of the non-uniform and concurrent memory access scheme prohibits the full utilization of the system potentials. Classical Worst Case Execution Time (WCET) estimation techniques upper bound the memory accesses -considering a fully congested memory bus - resulting in safe, but pessimistic, bounds. The proposed approach explores the increase in the system utilization by less critical tasks, while guaranteeing the safety of the critical task.

Published
2013

50. The WCET Tool Challenge 2011

Author

Hanxleden, Reinhard von, Holsti, Niklas, Lisper, Björn, Gustafsson, Jan, Islam, Nazrul Mohammad, Ploedereder, Erhard, Fellger, Wolfgang, Gepperth, Sebastian, Krause, Felix, Wilhelm, Reinhard, Bonenfant, Armelle, Casse, Hugues, Michiel, Marianne de, Rochange, Christine, Bünte, Sven, Huber, Benedikt, Kovacs, Laura, Puffitsch, Wolfgang, Zolda, Michael, Zwirchmayr, Jakob, Kästner, Daniel, Wegener, Simon, Kirner, Raimund, Olesen, Mads Christian, Prantl, Adrian, and Schoeberl, Martin

Abstract

Following the successful WCET Tool Challenges in 2006 and 2008, the third event in this series was organized in 2011, again with support from the ARTIST DESIGN Network of Excellence. Following the practice established in the previous Challenges, the WCET Tool Challenge 2011 (WCC'11) dened two kinds of problems to be solved by the Challenge participants with their tools, WCET problems, which ask for bounds on the execution time, and ow-analysis problems, which ask for bounds on the number of times certain parts of the code can be executed. The benchmarks to be used in WCC'11 were debie1, PapaBench, and an industrial-strength application from the automotive domain provided by Daimler AG. Two default execution platforms were suggested to the participants, the ARM7 as \simple target" and the MPC5553/5554 as a \complex target," but participants were free to use other platforms as well. Ten tools participated in WCC'11: aiT, Astree, Bound-T, FORTAS, METAMOC, OTAWA, SWEET, TimeWeaver, TuBound and WCA.

Published
2012

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