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This paper presents upset rates of flip-flops in 65 nm commercial bulk technology predicted through modeling, and compares the predictions to upset rates measured with thorium foil, 15 MeV carbon ions, and 148 MeV protons. This paper demonstrates that 15 MeV carbon ions can be used to emulate the daughter products of neutron spallation reactions. Index Terms--Flip-flop, single-event upset (SEU), soft error.

Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed. Index Terms--Proton irradiation, silicon-on-insulator (SOI) technology, single event upset (SEU), SRAM.

Experimental data are presented showing that low energy (< 2 MeV) proton irradiation can upset exploratory 65 nm node, Silicon-On-Insulator circuits. Alpha particle SER data, modeling and simulation results provide a plausible mechanism. This work suggests that track structures need to be understood and effectively modeled, especially for small, modern devices. Index Terms--Alpha particles, direct ionization, protons, radiation effects, simulations, soft error rate.

Novel techniques have been developed to simulate particle transport in arbitrarily complex back-end-of-line topologies. They are shown to be critical for single event effect analyses of new device structures for 65 nm CMOS technologies and beyond. The salient features of the new modeling methods are illustrated by the simulation results taken from several case studies of particle-induced radiation problems in the back end. Index Terms--Alpha-particle radiation effects, energy deposition, ion radiation effects, radiation effects, simulations, single event effect, single event upset, soft fail rate.

This paper describes techniques for mitigating single event upsets in master-slave flip-flop latches in 65 nm SOI device technology. Techniques are explained, modeled, and measured with hardware experiments. Index Terms--Alpha particle, modeling, radiation event, single event upset (SEU), soft error.

Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled. Index Terms--Critical charge, Qcrit, SER, single event upsets, SOI.

The use of state-of-the-art microelectronic devices in space radiation environments faces new challenges with the adoption of low dielectric constant (low-k) materials as inter-level dielectrics. This is demonstrated in a preliminary study of methyl-silsesquioxane low-k films. We report radiation damage, induced by a 2-keV low- current-density (~2 x [10.sup.6] [s.sup.-1] [cm.sup.-2]) positron beam, and observed by positron annihilation spectroscopy. Index Terms--Dielectric, electron radiation, ionizing radiation, low dielectric constant (low-k), polymer.

Research was conducted to examine low dielectric constant (low-k) hydrogen-silsesquioxane (HSSQ) thin films using Doppler broadening positron annihilation spectroscopy. Changes in the local electronic environment in a thin film were observed via the high void sensitivity of the method in combination with depth-resolving capability. Results suggest a complex relationship between the film dielectric constant and pore size and pore density.

Copper‐plated interconnects were widely adopted for volume manufacture of integrated circuits after more than a decade of intensive research to demonstrate that use of Cu would not impact device reliability. However, although Cu‐plated metallisation promises significantly reduced costs for Si photovoltaics, its adoption in manufacturing has not gained the same traction. This review identifies some key challenges facing the introduction of Cu‐plated metallisation for Si photovoltaics. These include the following: (1) increased carrier recombination due to the use of Cu for metal contact formation; (2) reduced module reliability due to adhesion or contact integrity failures; and (3) limited availability of cost‐effective processes and equipment for metal plating. For integrated circuits, Cu's low electrical resistance and high resistance to electromigration provided an impetus for the large investment in process development that was required to realise Cu‐plated interconnects. However, the technical advantages of using Cu for Si solar cell contacts are not as compelling, as solar cells can tolerate larger feature sizes thus reducing the criticality of the contact metal's conductivity and electromigration properties. Additionally, for Si photovoltaics, low cost is paramount, and new challenges arise from the need for modules to absorb light and operate in the field for 25+ years in diverse outdoor climates. However, with the scale of Si photovoltaic manufacturing expected to increase dramatically in the next decade, the use of large quantities of silver for cell metallisation will provide an incentive to address reliability concerns regarding the use of Cu for Si photovoltaic metallisation. Copper‐plated interconnects were widely adopted for volume manufacture of integrated circuits after more than a decade of intensive research. However, although Cu‐plated metallisation promises significantly reduced costs, its adoption in Si photovoltaic manufacturing has not gained the same traction. This review identifies some key challenges facing the introduction of Cu plating for Si photovoltaics and in particular discusses (1) increased carrier recombination due to Cu, (2) reduced module reliability, and (3) limited availability of cost‐effective processes and equipment for metal plating. [ABSTRACT FROM AUTHOR]