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Analytical target cascading (ATC) is a method developed originally for translating system-level design targets to design specifications for the components that comprise the system. ATC has been shown to be useful for coordinating decomposition-based optimal system design. The traditional ATC formulation uses hierarchical problem decompositions, in which coordination is performed by communicating target and response values between parents and children. The hierarchical formulation may not be suitable for general multidisciplinary design optimization (MDO) problems. This paper presents a new ATC formulation that allows nonhierarchical target-response coupling between subproblems and introduces system-wide functions that depend on variables of two or more subproblems. Options to parallelize the subproblem optimizations are also provided, including a new bilevel coordination strategy that uses a master problem formulation. The new formulation increases the applicability of the ATC to both decomposition-based optimal system design and MDO. Moreover, it belongs to the class of augmented Lagrangian coordination methods, having thus convergence properties under standard convexity and continuity assumptions. A supersonic business jet design problem is used to demonstrate the flexibility and effectiveness of the presented formulation. [DOI: 10.1115/1.4001346]

Testing complex systems, such as the ASML TWINSCAN lithographic machine, is expensive and time consuming. In a previous work, a test sequencing method to calculate time-optimal test sequences has been developed. Because complex systems are composed of several subsystems, which are again composed of several modules, there exists a need to hierarchically model test sequencing problems. Such a hierarchical test sequencing problem consists of a high-level model that describes a test sequencing problem at the system level, and one or more low-level models that describe the test sequencing problems at the subsystem or module level. The tests at the system level correspond to the solutions of low-level problems. This paper describes a hierarchical test sequencing model and proposes two algorithms to compute an optimal test sequence. The benefits of hierarchically modeling a problem are less computational effort and less modeling effort, because not all relations are needed. This is illustrated by a small example. The industrial relevance of this method is illustrated on a case study related to a manufacturing testing phase of a lithographic machine. Index Terms--Hierarchical test sequencing, manufacturing systems, semiconductor manufacturing industry, Tangram, test strategy.

The integration and test phase of complex manufacturing machines, like an ASML lithographic manufacturing system, is expensive and time consuming. The tests that can be performed at a certain point in time during the integration phase depend on the modules that are integrated and, therefore, on the preceding integration sequence. In this paper, we introduce a mathematical model to describe an overall integration and test sequencing problem, and we propose an algorithm to solve this problem. The method is a combination of integration sequencing and test sequencing. Furthermore, we introduce several strategies that determine when test phases should start. With a case study within the development of a software release that is used to control an ASML lithographic machine, we show that the described method and strategies can be used to solve real-life problems. Index Terms--Integration, manufacturing machines, semiconductor industry, test sequencing, test strategy.

Testing complex manufacturing systems, like ASML lithographic machines, can take up to 45% of the total development time. The decision of when to stop testing is often difficult to make because less testing may leave critical faults in the system, while more testing increases time-to-market. In this paper, we solve the problem of deciding when to stop testing by introducing a test-sequencing method that incorporates several stopping criteria. These stopping criteria consist of objectives and constraints on the test cost and the remaining risk cost. For a given problem, a suitable stopping criterion can be chosen. For example, with the risk-based stopping criterion, testing stops when the test time or cost exceeds the risk cost. Furthermore, we show that it also is possible to model reliability problems with this test-sequencing method. The method is demonstrated on ASML systems with two case studies. The first case study was conducted in the test phase during the development of the software that is used to control an ASML lithographic machine. The second case study was conducted on the reliability testing of a lithographic machine. Index Terms--Manufacturing systems, reliability testing, semiconductor manufacturing industry, system testing, TANGRAM, test sequencing.

An Effective Process Time (EPT) approach is proposed for the building of aggregate models to represent multi-server tandem queues with finite buffers. EPT distributions of the workstations in the flow line are measured without identifying the contributing factors. A sample path equation is used to compute the EPT realizations from arrival and departure events of lots at the respective workstations. If the amount of blocking in the line is high, the goodness of fits of the EPT distribution determines the accuracy of the EPT-based aggregate model. Otherwise, an aggregate model based on just the first two moments of the EPT distributions is sufficient to obtain accurate predictions. The approach is illustrated in an industrial case study using both simulation and analytical queueing approximations as aggregate models. Keywords: Aggregate modeling, analytical queueing approximation, blocking, discrete-event simulation, effective process time, finite buffer capacity, performance analysis, 1. Introduction Multi-server tandem queues with finite buffers commonly occur in industrial practice. The performance of these lines is typically expressed in terms of throughput and flow time. Irregularities in [...]

Testing complex manufacturing systems, such as an ASML lithographic machine, takes up to 45% of the total development time of a system. The problem of which tests must be executed in what sequence to ensure in the shortest possible test time that the system works, which is the test-sequencing problem, was already solved by Pattipati et al. for the diagnosis of systems during operation. Test-sequencing problems during the development and manufacturing phases of systems, however, require a different approach than the test-sequencing problems during operation. In this paper, the test problem description and algorithms developed by Pattipati et al. are extended to solve test-sequencing problems for the development and manufacturing of manufacturing systems. For a case study in the manufacturing process of an ASML lithographic machine, it is shown that solving a test-sequencing problem with this method can reduce the test time by 15% to 30% compared to experts that solve this problem manually. Index Terms--AND/OR graphs, manufacturing systems, semiconductor industry, TANGRAM, test sequencing, test strategy.

One of the present developments in the semiconductor industry is integration of metrology tools in the main process tool, instead of measuring wafers stand-alone, i.e., at an offline metrology tool. One of the advantages expected from integrated metrology (IM) compared to offline metrology (OM) is an earlier detection of out-of-control situations in the process tool. Despite of the advantages expected from IM, manufacturers will only convert to IM if investments can be justified. The objective of this paper is to compare the effect of process failures in the processes on the performance of a workstation using OM or IM. Analytical relations for effective process time and flow time of a workstation, containing a single machine or a cascade machine, are derived and validated for both OM and IM. In the analysis, the performance of OM and IM practices are compared and the influence of process failures is investigated. It can be concluded that a workstation containing a single machine or a cascade machine with IM outperforms a workstation with OM with respect to flow time for lower levels of utilization. For higher levels of utilization the effective (maximal achievable) throughput of a workstation with IM is limited because of the increase of the process time by the quality measurement time. If the frequency of process failures is reduced by improving the workstation, a better performance of a workstation with OM is obtained with respect to flow time and throughput at higher utilization levels. In all situations, a workstation with OM and no transport time (inline metrology) has the best flow time performance. The opinion in industry that IM has a positive influence on flow time performance is not shared by the results of this paper. The results are obtained, e.g., by making no distinction between different metrology inspections or by neglecting the influence of a metrology module upon the reliability of the workstation. In practice, metrology configurations may not perform equally so that a preference for one of them might be based on other considerations than flow time performance. Index Terms--Effective process time, metrology, performance measures, semiconductor manufacturing systems, variability.

Based upon basic drivers for the flow time, a lumped parameter model for a manufacturing line has been derived by using Kingman's approximation. The lumped parameter model for the flow time consists of a workstation and delay time. The workstation is characterized by the effective process time of the bottleneck workstation and the weighted sum of the coefficients of variation of all workstations. The delay time is determined by the sum of all effective process times of the nonbottleneck workstations. The advantage of the application of the lumped parameter model is that the variability of the total line is determined by a measurement at the operating point of the actual manufacturing line. This variability depends upon the operating point. Examples show that this dependency is not too strong for lines with a distinct bottleneck workstation in the actual line. From the derivation of the lumped parameter model it can be concluded that an improvement of the effective process time of the bottleneck workstation of the line results in an increase of the total variability of the line. This variability can be reduced by either reducing the variability of all workstations or the effective process times of the nonbottleneck workstations. Index Terms--Lumped parameter model, manufacturing systems, performance, variability.

Process time variability plays a key role in the cycle time of wafers. Several sources of variability can be distinguished. However, identification and measurement of all individual sources is almost impossible. Therefore, in previous work, a new method has been proposed to measure effective process times (EPT) for single-lot machines. The EPT incorporates the various sources of variability. From the measured EPT realizations, the mean and the corresponding coefficient of variation can be computed for queueing performance analysis. This paper follows up on previous work. The EPT quantification approach is generalized toward batching equipment. The batching types of operations are commonly present in the semiconductor industry. The paper proposes a transformation algorithm that transforms lot events into batch events. This enables one to use the previously developed single-lot algorithm also for batch machine workstations. An industry case illustrates the approach using operational data of furnace workstations. Index Terms--Batching, capacity and cycle time losses, equipment modeling, factory dynamics, furnaces, manufacturing data processing, manufacturing line performance, queueing analysis.

To remain competitive and to boost profitability, manufacturers in capital-intensive and highly competitive industries want to maximize throughput and minimize flow time. Achieving high throughput conflicts with achieving low flow time. In order to unhide the tradeoff between throughput and flow time, a performance measure, called manufacturing performance, has been developed. The manufacturing performance is defined by the quotient of the ratio between throughput and flow time of an actual manufacturing system and this ratio of a reference system. The reference system can be adapted by the user in correspondence with objectives. By applying the manufacturing performance to one workstation and using analytic approximations for this workstation, manufacturing performance can be expressed analytically. It seems that manufacturing performance has an optimal value that is given by equipment availability and coefficient of variation. Manufacturing performance is applied also to a four-workstation manufacturing line. Results from analytic approximations show the practicability of the manufacturing performance. Comparison of manufacturing performance with overall fab efficiency, an earlier proposed metric, showed that the manufacturing performance is a more clear metric. This conclusion was based upon simulations with a two-stations manufacturing line. The manufacturing performance is a technical performance metric for manufacturing lines that supports, for instance, economical considerations to obtain optimal throughput-flow time combinations under economical optimal results. This is a useful addition to the existing metrics, which may benefit manufacturers in their operations. The authors consider this contribution as a discussion paper and demand for comment. Index Terms--Fab performance, manufacturing performance, overall fab efficiency (OFE), performance measures.

Overall equipment effectiveness (OEE) is a metric that has been accepted completely in the semiconductor industry. OEE is simple and clear, and standards and guidelines have been developed. Nonetheless, literature indicates imperfections in applying OEE with regard to time base and rate efficiency. As literature lacks a basic framework for OEE, effectiveness has been approached systematically that resulted in a new equipment effectiveness E. The main difference between OEE and E concerns the choice of the time base. OEE does include equipment-independent conditions, such as lack of input items. This condition is not caused by the equipment but by the environment of the equipment. E has been defined to get a performance measure that is related to equipment-dependent states only, viz. effective state consisting of productive state, scheduled down state, and unscheduled down state. Because of the stand-alone condition, the equipment effectiveness expresses the (equipment) internal losses, while utilization expresses the external losses. By using E, equipment can be compared and improved. It can be concluded that the advantage of E over OEE is that real equipment effectiveness is measured as the influence of utilization (equipment-independent conditions) is eliminated. Index Terms--Overall equipment effectiveness (OEE), overall equipment efficiency, performance measures, semiconductor industry, state model.

Operational time variability is one of the key parameters determining the average cycle time of lots. Many different sources of variability can be identified such as machine breakdowns, setup, and operator availability. However, an appropriate measure to quantify variability is missing. Measures such as overall equipment effectiveness (OEE) used in the semiconductor industry are entirely based on mean value analysis and do not include variances. The main contribution of this paper is the development of a new algorithm that enables estimation of the mean effective process time [t.sub.e] and the coefficient of variation [c.sup.2.sub.e] of a multiple machine workstation from real fab data. The algorithm formalizes the effective process time definitions as known in the literature. The algorithm quantifies the claims of machine capacity by lots, which include time losses due to down time, setup time, and other irregularities. The estimated [t.sub.e] and [c.sup.2.sub.e] values can be interpreted in accordance with the well-known G/G/m queueing relations. Some test examples as well as an elaborate case from the semiconductor industry show the potential of the new effective process time algorithm for cycle time reduction programs. Index Terms--Capacity and cycle time losses, data extraction, equipment modeling, factory dynamics, manufacturing line performance.