Search

Accurate modeling and efficient parameter extraction of a small signal equivalent circuit of MOS transistors for high-frequency operation are presented. The small-signal equivalent circuit is based on the quasi-static approximation which was found to be adequate up to 10 GHz for MOS transistors fabricated by a 20 GHz cutoff frequency technology. The extrinsic components and substrate coupling effects are properly included. Direct extraction is performed by Y-parameter analysis on the equivalent circuit in the linear and saturation regions of operation. A low-noise amplifier is used to illustrate the effects on circuit performance due to accurate inclusion of extrinsic components in the model. Good agreement between simulated results and measured data on high-frequency transistor characteristics has been achieved.

A unified modeling approach for the submicrometer MOS transistor charge/capacitance characteristics in all operation regions is presented. Development of this MOS charge model is based on the charge-density approximation to reduce the complexity of the analytical expression. To model the charge density more accurately, the conductance-degradation coefficient is determined by the derivative of drain-to-source saturation voltage with respect to gate-to-channel potential. The unified charge densities in gate, channel, and bulk regions are obtained with the assistance of the sigmoid, hyperbola, and exponential interpolation techniques. Good agreement between the measurement data and simulation results is obtained.

A unified approach for the MOS transistor drain current modeling through all the operation regions is presented. Instead of the direct sum approach, the proposed use of interpolation and sigmoid functions can unify the drain current expression including the drift and diffusion components for the weak- and strong-inversion regions. This approach results in a differentiable continuity in conductances with respect to the gate, drain, and bulk bias voltages. As verified by the experimental data, the model shows an accurate prediction capability for the transconductance and output conductance characteristics in both strong- and weak-inversion regions.

A unified single-equation approach for the MOS transistor drain current modeling for energy-efficient submicron MOS circuits is presented. Instead of three sets of separate equations for the triode, saturation, and weak inversion regions, only a continuous expression which is valid to describe the behavior of drain current and the derivatives in all operation regions can be realized by using a combination of hyperbola, sigmoid, and interpolation methods. The model expression can predict accurate results for the current, output conductance, and transconductance with continuous and smooth characteristics. The simulation results agree well with experimental data.

In order to meet the requirements for multimedia applications, several approaches to DRAM architecture have emerged. Instead of a single, common memory device, several advanced approaches, such as extended data out (EDO) DRAM, and synchronous DRAM (SDRAM) will each play a major role in the future memory market. Furthermore, advanced interface technologies, such as Rambus RAM (RDRAM), RamLink, and SyncLink are very promising for future-generation memory. Also, application-specific memory, such as cache DRAM (CDRAM), enhanced DRAM (EDRAM), and video DRAM (VRAM) offer unique characteristics to improve performance in particular applications. Since it is beneficial to understand which type of high-speed memory can improve the speed performance of a particular system most effectively, this article discusses the fundamental concepts of these recent high-speed performance memory architectures to aid in the selection of memories for multimedia applications.

An efficient MOSFET modeling methodology with statistical optimization has been introduced to facilitate advanced mixed-signal circuit design. Based on the properties of the S- CMOS model, a combination of local optimization and the group-device extraction strategy is adopted for parameter extraction. By using the statistical method with an Excel solver, a very accurate parameter extraction procedure was developed for the S-CMOS model and was implemented with the optimization software. An accurate parameter set is extracted in accordance with the measurement data of TSMC 0.35-/spl mu/m technology from MOSIS Service with the LMEE method. The S-CMOS model was implemented into a SPICE3f3 simulator. Several analog and digital circuits were simulated using the popular BSIM3v3 and compared with the S-CMOS model.

A single-equation approach as an extension to the EKV MOS transistor model, to realize the drain current modeling characteristics for low-voltage MOS circuits is presented. Instead of three sets of separate equations in the triode, saturation, and weak inversion regions, only a single expression which is valid to describe the drain current behavior in all the transistor operation regions can be realized by using hyperbola and interpolation techniques. Since all the terms and the derivatives in this expression are continuous, this single-equation can predict good results for the current, output conductance, and transconductance with continuous and smooth characteristics.

A unified modeling approach for the submicron MOS transistor charge/capacitance characteristics in all operation regions is presented. The development of the MOS charge model is based on the charge density approximation to reduce the complexity of the expression. The unified charge densities in gate, channel, and bulk are obtained with assistance of the sigmoid, hyperbola, and exponential interpolation techniques. By carrying out the integration of the charge densities along the channel area, the terminal charges associated with gate and bulk can be obtained. The non-reciprocal capacitance behavior is well realized in this model. Good agreement between the measurement data and simulation results is obtained.

The architecture and the components design of a compact VLSI model based on the extension of the cellular neural network paradigm is described. Face and image recognition is an important function in future smart, portable multimedia systems. However, it involves many complicated mathematical operations that requires extremely large computing power. Since most operations are in two-dimensional format, the cellular neural network paradigm can be extended for selective tasks in face recognition function. Compact neural network is a suitable computing architecture. It uses the state-constrained neuron model that prevents the state variables becoming unbounded. The clear advantage is that the network will converge to proper solutions quickly. In addition, the hardware annealing technique can be applied to the compact neural network architecture so that the optimized solution can be quickly obtained without the drawback of conventional simulated annealing searching complexity and time penalty.

In this paper, we present a compact CMOS VLSI design for recursive neural networks with the capability of hardware annealing. Locally-connected recursive neural networks are a class of analog nonlinear networks which can solve many important optimization, and signal processing problems and is suitable for VLSI implementation because of its low demand on inter-cell connections. Hardware annealing, which is a paralleled version of effective mean-field annealing in analog networks, is a highly-efficient method to find global optimal solutions of recursive neural networks. A two-neuron prototype chip to demonstrate the functionality of hardware annealing is designed, analyzed and implemented in 2.0 /spl mu/m CMOS technology using mixed-signal design methodology through MOSIS. For circuit reliability and compactness, a unit current of 6 /spl mu/A is used. The cell density is 505 cells/cm/sup 2/ and the cell time constant time is designed to be 0.3 /spl mu/s. Laboratory experimental results to show the behavior of this two neuron chip was produced with annealing control signals from a function generator.