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This paper addresses the challenge of efficiently designing multiplexer structures in quantum-dot technology circuits. Specifically, it introduces a novel approach to constructing a 2-to-1 multiplexer through a unique gate design that relies on the interaction between cells. The key focus of this design is to minimize the utilization of cells, thereby conserving space and facilitating the creation of more complex combinational and sequential circuits. The methodology involves developing a gate structure that requires the least number of cells compared to existing designs. This reduction in cell usage not only optimizes space utilization but also enhances the scalability of the multiplexer for integration into larger circuits. The proposed gate structure demonstrates a significant improvement, achieving a 15% reduction in the number of cells compared to the previously best-known design. To further evaluate the effectiveness of this novel gate design, the study extends its analysis to include the implementation of various complex circuits such as a 4-to-1 multiplexer, D latch, and T latch. These structures are synthesized using the newly proposed gate design as a fundamental building block. To validate the functionality and performance of these circuits, simulations are conducted using the QCADesigner simulation tool. This comprehensive simulation enables a thorough assessment of the proposed structures across different circuit configurations, providing insights into their operational efficiency and suitability for practical applications in quantum-dot technology. [ABSTRACT FROM AUTHOR]

In this paper, we design and simulate a novel, highly compact and power-efficient silicon-based JK flip-flop (JKFF) employing an engineered gate technique, for the first time. Herein, the pull-down and the pull-up paths used to realize the JKFF have been realized by 4 and 2 engineered gate transistors, respectively (total six), whereas 8 pull-ups and 8 pull-down (total 16) transistors are used to realize the JK flip-flip in the conventional MOS technology. Two-dimensional (2D) calibrated mixed-mode simulations have revealed substantial improvement in various performance measuring parameters of the proposed JK flip-flop. The proposed technique has resulted in a significant reduction of 62.5% in transistor count, ∼9.12% in power consumption, 2.5% decrease in delay and 11.38% in power delay product in comparison to the conventional JKFF realization. Further, the proposed gate-engineered JKFF has been used to realize highly compact D and T flip-flops. It has been observed that a 55.5% and 62.5% decrease in transistor count have been achieved in comparison to the conventional MOS-based JKFF realization of D and T flip-flops, respectively. A significant improvement in power consumption, delay, and power delay products has been achieved in the proposed D and T flip-flops in comparison to the conventional JKFF-based D and T flips. It has been observed that notably, the versatility of this approach allows for straightforward adaptation to realize various other sequential and combinational circuits. Besides, the process flow for the fabrication of the proposed engineered gate transistors for realizing the JKFF, D and T flip-flops has also been given. [ABSTRACT FROM AUTHOR]

The logic structures implemented in Field Programmable Gate Arrays (FPGAs) are often critical and their correct operation is vital. FPGA devices are often used in areas where there is increased ionising radiation (space, medical diagnostics, aviation or nuclear power). There is therefore a need for mechanisms to correct radiation-induced errors. A common approach is the redundant implementation of particularly critical parts of the logic structure. By triplicating selected fragments, it is possible not only to detect potential errors but also to correct them. Such an approach is called triple modular redundancy (TMR), and its essence lies in the use of specialised voting circuits called voters, which allow the erroneous results of individual subcircuits to be eliminated by voting. The triplicate circuit under consideration, together with the voter, constitutes the mitigation structure. It becomes necessary to develop a test environment to assess the correct operation of these circuits. Also key is the efficiency of the implementation of these structures, which can be related to the occupation of logical resources or the power consumption of a given implementation. This paper demonstrates the essence of implementing a test environment to test the correctness of the mitigation of logic structures using TMR voters. An error injector mechanism using the Pseudo-Random Bit Sequence (PRBS) register is proposed, which introduces an element of randomness into the testing process. The aim of this research is to determine the implementation efficiency of the proposed test environment. In the experimental part, the implementation costs of the proposed solution were examined. The results indicate that between 66 and 109 LUT blocks were required to implement the error injector, corresponding to a relatively small increase in dynamic power consumption: by 22% for combinational circuits and by 37% for sequential circuits. [ABSTRACT FROM AUTHOR]

Considering the growing trend toward reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers. One of the solutions to reduce power consumption is the design of reversible circuits. This paper proposed the design of a low-cost self-control serial adder system. In the proposed circuit, EPOE expressions have been used for the direct and compact design of sequential circuits to reduce the fixed inputs of sequential logic circuits. In addition, to reduce the quantum cost, common terms between the outputs are optimally used. Also, limiting the use of Tofoli gates with a size larger than three inputs in the implementation of the final circuit will reduce the quantum cost of the resulting circuit. The results and comparisons showed that the proposed design has improved efficiency measures including quantum cost, garbage outputs, and fixed inputs compared to existing works. [ABSTRACT FROM AUTHOR]

Understanding how neural circuits generate sequential activity is a longstanding challenge. While foundational theoretical models have shown how sequences can be stored as memories in neural networks with Hebbian plasticity rules, these models considered only a narrow range of Hebbian rules. Here, we introduce a model for arbitrary Hebbian plasticity rules, capturing the diversity of spike-timing-dependent synaptic plasticity seen in experiments, and show how the choice of these rules and of neural activity patterns influences sequence memory formation and retrieval. In particular, we derive a general theory that predicts the tempo of sequence replay. This theory lays a foundation for explaining how cortical tutor signals might give rise to motor actions that eventually become "automatic." Our theory also captures the impact of changing the tempo of the tutor signal. Beyond shedding light on biological circuits, this theory has relevance in artificial intelligence by laying a foundation for frameworks whereby slow and computationally expensive deliberation can be stored as memories and eventually replaced by inexpensive recall. [ABSTRACT FROM AUTHOR]

The counters that change their transition using a clock signal are called synchronous counters. While designing a synchronous counter circuit, the power consumption and the delay are the major issues. Several synchronous counters were designed previously with the help of flip flops, but they did not provide good results. The existing synchronous counters increased power consumption and delay and decreased the speed. To overcome these issues, in this manuscript, a reversible synchronous counter is designed utilizing Multiple-Controlled Toffoli (MCT) and Multiple-Controlled Fredkin (MCF) reversible logic gates. Here, three JK flip-flop designs, such as JK1, JK2, and JK3 are designed for a reversible synchronous counter. Then JK1 and JK2 are structured by MCT. Whereas the JK3 flip-flop design is designed under MCF reversible logic gates. Coding is carried out Verilog, and then the proposed Reversible synchronous counter design (RSCD) is synthesized and implemented on FPGA using a Xilinx ISE 14.5 System generator. Here, performance metrics, such as delay, power, maximum counting rate, and total equivalent gate counts are examined. The efficiency of the proposed RSCD-MCT-MCF design attains gate counts of 23.45%, 28.94%, and 29.04% and is compared to the existing designs, such as Effective Designing of Reversible Synchronous Counters in Nanoscale (SCD-MTG), effective designing for reversible sequential circuits (SCD-3TG-4FG), designing of synchronous decimal counter utilizing reversible Toffoli–FredkinNetlist (SCD-TOF2). [ABSTRACT FROM AUTHOR]

In recent times, the multi-valued logic (MVL) design has been widely explored in the designing of digital computing circuits as the goals of enhanced processing capability with reduced interconnect complexity and small chip area are achieved. Hence, this work describes the design methodology of ternary logic-based asynchronous and synchronous up-counter, down-counter, and ring-counter designs using D-flip-flops in carbon nanotube technology. Carbon nanotube-field-effect transistors (CNTFETs)' unique feature of altering the device threshold voltage by making variations in CNT diameter is exploited for the realization of multiple voltages in ternary logic design. Here the principle of the master-slave scheme is adopted for the designing of Dual shift-single shift and Single shift-dual shift-D-flip-flop circuits using the cyclic property of shifting operators. These flip-flop designs are further extended to construct multiple-digit counter structures which are suitable for realizing the logic functionality of up-counter, down-counter, and ring-counter designs. To exploit ternary logic increased computation capability benefit, a mode control up/down counter circuit is designed in which a single module is generating up and down-counting sequence based on applied mode input. To investigate the performance of the proposed designs, the simulations are performed using the Synopsys HSPICE simulator considering the 32 nm Stanford CNTFET model. According to the simulation results, a maximum energy consumption reduction up to 55% is obtained compared to the counterpart. Hence, the increased computational capability of three-valued logic is exploited in the presented work to achieve energy enhancements in designing ternary sequential circuits. [ABSTRACT FROM AUTHOR]

Clock attacks and power attacks are used as common means to inject faults in embedded devices. Critical analysis of the properties and the components engaged with these fault injection methods is of high importance to assess the related dangers and furthermore to enhance the process of designing suitable counter-measures. This paper provides critical analysis of induced faults on combinational and sequential circuits and study effects of various attacks (over-clock, under clock, power attack). While doing analysis, it was revealed that clock attacks i.e., under and over clock attacks have similarity index of (80–90%). Also it was found that power attacks have results similar (60–70%) to clock attacks but they cause propagation delay in circuits affecting the output. Cadence virtuoso 45 nm technology node, Keil and Multi-sim software's were used to generate various attacks. The comparative analysis reveals that the attack timing and frequency of the glitch is the key while inducing fault injection attacks. While performing this work, it is observed the sequential circuits get less impacted by attacks comparing to combinational circuits. This research is conducted from an attacker's perspective instead of mitigation perspective. [ABSTRACT FROM AUTHOR]

Purpose: A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops. Design/methodology/approach: This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops. Findings: The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop. Originality/value: This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency. [ABSTRACT FROM AUTHOR]

The diminution of power dissipation has recently become a paramount concern in contemporary VLSI design. Owing to the shrinking chip size and the gradual development of several micro-electronic reliabilities, low-power (LP) system design has become the utmost priority. Hence, this paper proposes an effective power reduction method that combines clock gating (CG) and a multi-bit flip flop (MBFF) approach. Initially, the CG and MBFF schemes were implemented separately in two standard Johnson counters, one involving a true single-phase clock (TSPC) LP D flip flop (DFF) with five transistors and the other involving a standard DFF with 32 transistors. Furthermore, a combined CG-MBFF scheme is proposed and implemented in 4-bit and 16-bit Johnson counters to illustrate the superiority of the proposed CG-MBFF scheme in terms of power diminution over the CG and MBFF methods when implemented separately. Additionally, an LP application employing a 4-bit Johnson counter was implemented with and without the proposed scheme. [ABSTRACT FROM AUTHOR]

Testing modern integrated circuit (IC) is challenging with introduction of System-on Chip (SOC). Enormous test pattern count is required to authenticate the IC which inflates power consumption. Henceforth, it is mandatory to incorporate power minimization techniques at circuit design phase. Optimizing test patterns is one such effective technique that curtails test power without altering circuit design. In this paper, a new test pattern reordering algorithm is proposed based on Recurrent Neural Network. Hopfield Neural Network (HNN) constitutes an optimized solution for solving traveling salesman problem (TSP). Since, test pattern reordering can be interpreted as TSP, optimized test pattern order is attained with HNN. Energy function of this algorithm falls into local minimum, so to eradicate this issue, the algorithm is modified. Test patterns are reordered with minimal hamming distance among consecutive test patterns. The proposed algorithm is implemented in ISCAS'89 Sequential Benchmark circuits. Experimental results prove that significant reduction in transition count is accomplished with proposed algorithm without compromising fault coverage. [ABSTRACT FROM AUTHOR]

In recent years, non-volatile memory elements have become highly appealing for memory applications to implement a new class of storage memory that could replace flash memories in sequential logic applications, with features such as compactness, low power, fast processing speed, high endurance, and retention. The memristor is one such non-volatile element that fits the fundamental blocks of sequential logic circuits, the latch and flip-flop; hence, in this article, a non-volatile latch architecture using memristor ratioed logic (MRL) inverter and CMOS components is focused, with an additional memristor as a memory element. A Verilog-A model was used to create the memristor element. The simulation findings validated the compact, low-voltage, and reliable design of the latch design. We evolved in technology enough to create a master-slave flip-flop and arrange it to function as a counter and a shift register. Power, number of elements, cell size, energy, programming time, and robustness are compared to comparable non-volatile topologies. The proposed non-volatile latch proves non-volatility and can store data with a 24% reduction in power consumption and a near 10% reduction in area. [ABSTRACT FROM AUTHOR]

Logical gates have been used in implementation of logic sequential and combinational circuits especially in computers, DSPs and microprocessors. They are mostly fabricated based on CMOS technology that provides a few nano-seconds of delay for each digital gate. Due to limitations in more scaling CMOS transistors and cause of short channel effects, some engineers and researchers believe that there is a huge demand for new devices and fabrication technologies to produce faster logic gates. In this paper, a new architecture for NAND gate is presented which operates based on mechanical resonance of a network of weakly coupled resonators that resonate in radio frequencies. This design is achieved by employing the associative memory property of Hopfield neural networks and the theory of weakly coupled resonators. The main advantage of the proposed design is in its capability to reach out delay times of the order of 1 nano-seconds or even less. One solution to decrease the delay time can be increasing the resonance frequency of resonators which are processing elements of resonators network. In this paper just the new idea of implementation NAND gate based on weakly coupled RF MEMS resonators is presented and evaluated. Other criteria like gate power consumption, effects of temperature, fan in, fan out and noise margin are not discussed. Regarding the rapid growth in MEMS technology, resonators with super high frequency (SHF 3–30 GHz) are now available and those with Extremely High frequency (EHF 30–300 GHz) will soon be in market which enables the presented design to achieve higher speeds. In addition, mechanical resonators are more fault tolerant than CMOS circuits when utilized in harsh environments which exposed to ionic beams or electron beam radiations. In space applications, the satellite and payload are exposed to huge bombardments of space electrons and ions beams. So, the proposed NAND gate can be a good solution for enhancing reliability of devices and systems exposed to space radiations. [ABSTRACT FROM AUTHOR]

Safety-critical systems used in applications that demand high levels of dependability, efficiency, and fault-tolerance often use sequential logic circuits in its design and implementation. The safety-critical digital system typically uses latches, flip-flops, and other memory elements, which are prone to the effects of natural faults and single event upsets (SEUs) caused by radiation-induced effects. The faults can lead to subsystem failures due to the continuous advancement in the realization of the small size transistor. To design a reliable digital-based system, it is essential to develop new faulttolerance approaches that are integrated into the design of sequential logic circuits. This work proposes a novel fault-tolerant approach based on the redundancy of sequential logic circuit, which consists of a variety of design components, D flip-flop storage elements linked to a fault injection unit, a duplicate modular redundancy, and data monitoring units with a switching circuit. The experimental simulation results using a five-state Markov chain analysis model prove that the proposed fault-tolerant system can achieve 0.99999998 for reliability of the fault detection coverage (C) which equal to 0.99999. Finally, we believe that using this new approach of fault-tolerance and redundancy would improve the dependability and reliability of next generation safety-critical applications. [ABSTRACT FROM AUTHOR]

In this work, bottom‐up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top‐down fabricated nanosheet (NS) and multi‐wire (MW) reconfigurable field‐effect transistors (RFETs). Evaluating the key parameters of these transistors regarding the on‐ and off‐currents as well as threshold voltages for n‐ and p‐type operation exhibit a high degree of symmetry. Most notably also a low device‐to‐device variability is achieved. In this respect, the investigated Al–Si material system reveals its relevance for reconfigurable logic cells obtained from Si NSs. To show the versatility of the proposed devices, this work reports on a combinational wired‐AND gate obtained from a multi‐gate RFET. Additionally, up‐scaling the current is achieved by realizing a MW RFET without compromising reconfigurability. The Al–Si–Al platform has substantial potential to enable complex adaptive and self‐learning combinational and sequential circuits with energy efficient and small footprint computing paradigms as well as for native components for hardware security circuits. [ABSTRACT FROM AUTHOR]

Conventional sense amplifiers limit the performance of current RRAM computing-in-memory (CIM) macro circuits, resulting in high latency and energy consumption. This paper introduces a multi-bit quantization technology low-latency voltage sense amplifier (MQL-VSA). Firstly, the multi-bit quantization technology enhances circuit quantization efficiency, reducing the number of operational states in conventional VSA. Secondly, by simplifying the sequential logic circuits in conventional VSA, the complexity of sequential control signals is reduced, further diminishing readout latency. Experimental results demonstrate that the MQL-VSA achieves a 1.40-times decrease in readout latency and a 1.28-times reduction in power consumption compared to conventional VSA. Additionally, an 8-bit input, 8-bit weight, 14-bit output macro circuit utilizing MQL-VSA exhibited a 1.11times latency reduction and 1.04-times energy savings. [ABSTRACT FROM AUTHOR]

Stimulus-specific adaptation (SSA), the reduction of neural activity to a common stimulus that does not generalize to other, rare stimuli, is an essential property of our brain. Although well characterized in adults, it is still unknown how it develops during adolescence and what neuronal circuits are involved. Using in vivo electrophysiology and optogenetics in the lemniscal pathway of the mouse auditory system, we observed SSA to be stable from postnatal day 20 (P20) in the inferior colliculus, to develop until P30 in the auditory thalamus and even later in the primary auditory cortex (A1). We found this maturation process to be experience-dependent in A1 but not in thalamus and to be related to alterations in deep but not input layers of A1. We also identified corticothalamic projections to be implicated in thalamic SSA development. Together, our results reveal different circuits underlying the sequential SSA maturation and provide a unique perspective to understand predictive coding and surprise across sensory systems. [ABSTRACT FROM AUTHOR]

In this study, we endeavored to create and simulate a D‐type flip‐flop utilizing two‐dimensional photonic crystals featuring a square lattice. This flip‐flop, composed of just two intersecting waveguides, is both compact and straightforward. Constructed from 10 × 10 dielectric rods suspended in air, it boasts low output power in logic mode 0, creating a significant distinction between optical powers in modes 0 and 1, lending it a logical aspect. Optimized for operation at a communication wavelength of 1.55 µm, this flip‐flop proves suitable for optical communication systems. The third window optical fiber communication system is suitable for 1.55 μm wavelength because the fiber has the lowest loss. Our analysis involved calculating the band structure via the plane wave expansion method and determining the optical power distribution using the finite difference time domain method. [ABSTRACT FROM AUTHOR]

Organic field‐effect transistors switched by insulated gates are the most essential building blocks, while usually plagued with degraded gate control arising from complicated dielectric engineering. Subsequently, the resulting large supply voltage and power consumption remain an essential issue for portable electronics driven by a single battery of only 1.5 V. Herein, wafer‐scale organic Schottky‐gate transistor arrays using inkjet‐printed few‐layer organic semiconducting crystals are reported. The transistors exhibit steep switching characteristics with an average subthreshold swing of 55 mV per dec and high signal amplification efficiency over 45 S A‐1, attributed to efficient Schottky gating and enhanced charge injection. Thereafter, high‐gain inverters are successfully demonstrated with an ultralow power consumption of only 800 pW; also, they are integrated as 1 V driven sequential logic circuits. A coplanar double‐gate geometry is also introduced for low‐voltage, single‐device AND logic. Therefore, the work opens new avenues toward the sustainable advancement in single‐battery‐driven, ultralow‐power organic electronics. [ABSTRACT FROM AUTHOR]

This paper proposes an automated framework for test generation for digital circuits, using evolutionary algorithms (EAs) such as Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) targeting single stuck-at faults. The framework is built in MATLAB environment in conjunction with an open-source fault simulator HOPE. Finding the best test pattern with maximum fault coverage from a very large search space of digital tests is proven to be time effective in VLSI circuits using EAs. This work emphasizes upon finding the best test pattern with maximum fault coverage in fewer iterations. This indeed can significantly reduce the number of required test patterns to achieve a good fault coverage quickly. Unlike open source ATPG tool ATALANTA which can generate tests only for combinational circuits, our EA based test generation framework is able to generate test pattern for combinational as well as sequential circuits. The proposed framework has introduced test generation for sequential circuits before and after their "netlist cutting". In this context, an automated tool which can perform "netlist cutting" for sequential circuits without altering the structure of combinational logic has been devised. The quality of generated test patterns is verified through fault simulation of some of the ISCAS'85 combinational and ISCAS'89 sequential benchmark circuits. The work has also explored the efficacy of the best test pattern through variations of genetic operators like crossover and mutation rate. Results show that the proposed GA and PSO outperforms the commonly known open source ATPG tool ATALANTA. [ABSTRACT FROM AUTHOR]

Nowadays to process information on high speed and to reduce the complexity of digital devices, optical digital computational techniques are required. Many complex signal processing functions such as multiplexing, optical switching, addressing, coding/decoding are implemented using optical digital computational techniques. Optical logic gates are one of the most essential computational elements to design combinational and sequential circuits in optical signal processing. In this paper, all optical logic gates are designed with optimized structure of 2 × 2 Mach–Zehnder interferometer optical switch using Ti:LiNbO3 based waveguide at 1.46 µm employing electro-optic effect. Different design structures to realize all-optical logic gates are presented and compared with the previously designed optical logic gates. The mathematical description of all optical logic gates using cascaded structure of Mach–Zehnder interferometer switch is also defined. The performance parameters of designed optical logic gates have been analyzed by beam propagation method and the obtained results are verified by MATLAB. [ABSTRACT FROM AUTHOR]

The augmented electromagnetic railgun has demonstrated more potent electromagnetic force, a low excitation current, and less rail thermal damage, showing good potential in heavy load launch. However, the augmented railgun's load characteristics differ from the conventional double-rail railgun. In the augmented railgun launching experiment, it was found that the fly-wheel diode was damaged, and the capacitive power supply could not discharge fully, which led to residual energy and lower energy utilization. This paper began with the characteristics of the sequential trigger circuit, followed by the causes of the above faults, as well as the corresponding solutions. Based on the conventional excitation circuit, fault detection experiments were carried out first, and the fault mechanism was clarified. Furthermore, according to the solutions proposed, the conventional excitation circuit was improved so that it can work normally when a heavy inductance was loaded. Finally, the sequential trigger experiment was carried out again with the same circuit parameters. The research results showed that the fly-wheel diode could work normally after the circuit was improved, and the problem of residual energy could also be solved effectively. Moreover, the output performance was almost unaffected. [ABSTRACT FROM AUTHOR]

We construct a new procedure for clustering partially masked images from wafer bin maps (WBMs). A WBM is an image of bin codes from circuit probe tests on a wafer after a semiconductor manufacturing process. Certain defect patterns of WBMs provide engineers with information to isolate manufacturing problems. The engineers prefer to see the identified defect patterns in clusters. Then they may match each cluster to a well-known defect type or they could easily see if there are new defect patterns. However, the WBMs may be masked at a large area due to the sequential circuit probe tests for bin codes. WBMs may also have various proportions of noise. There are two major contributions of this research. First, our method of locally iterative interpolation for the image reconstruction of masked WBMs will recover certain parts of the original patterns. Second, we proposed a new modified Radon transformation to extract features for better clustering of partly masked WBMs. We demonstrated our procedure on synthetic WBMs with various defect pattern types and levels of masking through a simulation study. The image patterns of WBMs during simulation were observed from a specific kind of real wafer product. [ABSTRACT FROM AUTHOR]

In this work, a novel structure of a double-gate MOSFET is proposed and simulated. The CMOS inverter action in a single device realized by combining p-mode and n-mode MOS transistors is presented. The main advantage of the proposed device is fewer transistors for implementing sequential and combinational circuits. The significant reduction of the transistors, while designing a combinational circuit, will enhance the electronic industry with less power consumption. In our proposed device, a single substrate is used in comparison to the conventional CMOS inverter. The proposed device reduces short channel effects at lesser channel length. For Lg= 50nm, the proposed device, as an inverter, offers a unique VTC curve, SNM, V-curve along with sound values of performance parameters individually for p-mode and n-mode. A significant reduction in the junctions, wells and oxide regions can be seen from the proposed inverter design. Besides the performance of the device, the fabrication steps and the layout of the DGMOSFET-I are also presented in work. [ABSTRACT FROM AUTHOR]

Flip-flop (FF) serves as a fundamental unit in various sequential logic circuits and complex digital electronic systems for generating, transforming, and temporarily storing digital signals. Nonvolatility plays a crucial role in FFs by ensuring instant data recovery after unexpected data loss. Nonvolatile flip-flop can quickly recover in a self-powered environment, making it suitable for application environments such as the Internet of Things (IOT). Unfortunately, most existing nonvolatile FFs (NVFFs) suffer from extended delays and high energy consumption during data backup and restore operations. In this paper, we propose two innovative voltage-controlled nonvolatile FFs (VC-FFs), namely VC-DFF (voltage-controlled D-FF) and VC-SRFF (voltage-controlled SR-FF), which address these challenges using voltage-controlled spin-orbit torque (VC-SOT) devices. The proposed designs are evaluated using a 40 nm CMOS process. Simulation results demonstrate that the proposed designs achieve significant improvements in write (recovery) energy consumption, with over 7.2× (1.54×) and 18.7× (2×) enhancements compared to their STT- and SOT-based counterparts, respectively. [ABSTRACT FROM AUTHOR]

D flip-flop (DFF) is the basic unit of sequential logic in digital circuits. However, because of an internal cross-coupled inverter pair, it can easily appear as a single event upset (SEU) when hit by high-energy particles, resulting in the error in the value stored in the flip-flop. On this basis, a new structure D flip-flop is proposed in this paper. This flip-flop uses an asymmetric scheme in which the master–slave latch adopts different hardening structures. By sacrificing circuit speed in exchange for stronger SEU fortification capability, the SEU threshold of this structure is improved by 10 times compared to traditional D flip-flops. It has also been compared with Dual Interlocked Storage Elements (DICEs), and it saves the area cost of six transistors compared to the DICE structure. Under the same operating conditions, the average power consumption and peak power consumption are, respectively, 9.8% and 18.8% lower than those of the DICE circuit, making it suitable for soft radiation environments where high circuit speed is not a critical requirement. [ABSTRACT FROM AUTHOR]

This paper presents a systematic student-level approach to assess the impact of problem-based learning on enhancing students' performance in an undergraduate Digital Logic Design course. The problem was assigned as a mini-project and chosen to strengthen the student's understanding of an advanced part of the course, namely the sequential logic design. The study included data from semesters where students were assigned projects and other semesters without projects. The proposed approach relies on dividing students into groups based on their academic performance level to study how the project impacts these groups' performance. A baseline performance metric was created at the beginning of the semester to classify the students into three groups. At the end of the semester, the students' groups were reassessed to capture performance changes. The results consistently showed improvement across all students' levels in the semesters where the project was conducted. While it is natural for students' performance to change between the beginning and the end of the semester, the results show that the percentage of students who improved their performance level has increased in semesters with a project compared to the semesters with no projects. Also, the percentage of students whose performance degraded by the end of the semester has decreased in the semesters with a project. These results were also supported by an independent student survey that confirmed the positive project impact on the students' grasp of sequential circuit design. [ABSTRACT FROM AUTHOR]

Introduction: This study investigates the impact of sequential extracorporeal treatments with oXiris® or CytoSorb® plus Seraph-100® on the clinical and laboratory parameters of critically ill COVID-19 patients with bacterial superinfection. Methods: Patients admitted to the intensive care unit with COVID-19, bacterial superinfection, and undergoing blood purification (BP) were enrolled in this prospective, single-center, observational study. "standard BP" with oXiris® or CytoSorb® were used in 35 COVID-19 patients with bacterial infection. Seraph-100® was added in 33 patients when available serially in the same oXiris® circuit or as sequential treatment with CytoSorb® as a sequential BP. Results: A significant reduction in SOFA score 3 days after treatment was observed in patients undergoing sequential BP (11.3 vs. 8.17, p < 0.01) compared to those undergoing "standard BP" (11.0 vs. 10.3, p > 0.05). The difference between the observed and expected mortality rate based on APACHE IV was greater in the sequential BP group (42.4% vs. 81.7%, p < 0.001) than the "standard BP" (74.2% vs. 81.7%, p > 0.05). Patients treated with sequential BP had a longer survival than those treated with "standard BP" (22.4 vs. 18.7 months; p < 0.001). Conclusions: The sequential approach may enhance the positive effect of BP on organ dysfunction among critically ill patients with COVID-19 and bacterial superinfection. [ABSTRACT FROM AUTHOR]

The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) is a technological approach to implement digital circuits with exceptionally high integration density, high switching frequency, and low energy dissipation. QCA circuits are a potential solution to the energy dissipation issues created by shrinking microprocessors with ultra-high integration densities. Current QCA circuit designs are irreversible, yet reversible circuits are known to increase energy efficiency. Thus, the development of reversible QCA circuits will further reduce energy dissipation. This paper presents novel reversible and irreversible sequential QCA set/reset (SR), data (D), Jack Kilby (JK), and toggle (T) flip-flop designs based on the majority gate that utilizes the universal, standard, and efficient (USE) clocking scheme, which allows the implementation of feedback paths and easy routing for sequential QCA-based circuits. The simulation results confirm that the proposed reversible QCA USE sequential flip-flop circuits exhibit energy dissipation less than the Landauer energy limit. Irreversible QCA USE flip-flop designs, although having higher energy dissipation, sometimes have floorplan areas and delay times less than those of reversible designs; therefore, they are also explored. The trade-offs between the energy dissipation versus the area cost and delay time for the reversible and irreversible QCA circuits are examined comprehensively. [ABSTRACT FROM AUTHOR]

Embryonic architecture that carries self-evolving design with fault tolerant feature is proposed for deep space missions. Fault tolerance is achieved in the embryonic architecture due to its homogeneous structure. The cloning of configuration data or genome data to all the embryonic cells makes each cell capable of selecting required cell function using selective gene. The primary digital circuits of avionics are implemented on the fabric, where the configuration data in Cartesian Genetic Programming (CGP) format is evolved through customized GA. The CGP format is preferred over LUT format for the circuit configuration data due to its fixed data size in case of modular design. Further the CGP format enables fault detection at embryonic cell level as well as logic gate level. The various combinational and sequential circuits like adder, comparator, multiplier, register and counter are designed and implemented on embryonic fabric using Verilog. The circuit performance is evaluated using simulation. The proposed PHsClone genetic algorithm (GA) design with parallel-pipeline approach is to achieve faster convergence. Four concurrent PHsClone GA executions (four parallel threads) achieve convergence for the 10 times faster for a 1-bit adder, and 3 times faster for a 2-bit comparator. [ABSTRACT FROM AUTHOR]

Flip-flops are the most used sequential elements in synchronous circuits, but designs based on latches can operate at higher frequencies and occupy less area. Techniques to increase the maximum operating frequency of flip-flop based designs, such as time-borrowing, rely on tight hold constraints that are difficult to satisfy using traditional back-end optimization techniques. We propose Mix & Latch, a methodology to increase the operating frequency of synchronous digital circuits using a single clock tree and a mixed distribution of positive- and negative-edge-triggered flops, and positive- and negative-level-sensitive latches. An efficient mathematical model is proposed to optimize the type and location of the sequential elements of the circuit. We ensure that the initial registers are not moved from their initial location, although they may change type, thus allowing the use of equivalence checking and static timing analysis to verify formally the correctness of the transformation. The technique is validated using a $\mathrm {28 \text {n} \text {m} }$ CMOS FDSOI technology, obtaining $\mathrm {1.33 X}$ post-layout average operating frequency improvement on a broad set of benchmarks over a standard commercial design flow. Additionally, the circuit area was also reduced by more than $\mathrm {1.19 X}$ on average for the same benchmarks, although the overall area reduction is not a goal of the optimization algorithm. To the best of our knowledge, this is the first work that proposes combining mixed-polarity flip-flops and latches to improve the circuit performance.

This paper presents a novel D-latch circuit using multi-state quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FET). The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. Spatial location is used to encode multiple logic states along with the carrier transport in mini-energy bands formed in GeOx-Ge/ SiOx-Si quantum dot superlattice (QDSL), and to obtain 8-states operation. The design is based on the 8-state inverter using QDC SWS-FETs in CMOS-X configuration. This could be a new paradigm for designing flip-flops and registering more complex sequential circuits. The proposed design leads to reduced propagation delay and a smaller Si footprint. [ABSTRACT FROM AUTHOR]

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks. The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs' capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost. [ABSTRACT FROM AUTHOR]

The output state of a sequential logic circuit is determined by both the input signal at that time and the original state of the circuit, so the ability of the sequential logic circuit to unveil history-dependent signals will contribute to our understanding of the ordered expression of genes. Here, we show a sequential logic circuit built on λ exonuclease, capable of detecting the relative sequence between inputs and inhibiting the second signal response when the first signal activates the corresponding output signal. The input can be used not only as an active signal but also as a control signal to activate the component of the λ exonuclease built to generate an inhibit strand, enabling cross-inhibition. The hydrolytic properties of λ exonuclease allow for orthogonal sequence design, which enables flexibility in sequence design. It has been experimentally demonstrated that λ exonuclease itself is catalytic and that a small amount of input can still provide good inhibition with the assistance of λ exonuclease. The sequential logic circuit we have designed can be modularly integrated into larger-scale circuits, to handle input sequence-related functions and lay the foundation for further understanding of ordered gene expression. [ABSTRACT FROM AUTHOR]

In this paper, a Quantum-Dot Cellular Automata (QCA)-based D -flip flop is designed with low quantum cost to propose a 3-bit sequence detector which detects a bit pattern 101 in both overlapping and non-overlapping forms. Initially, a level to edge-triggered clock converter is proposed to convert clock signal levels into edge defining signals. Later, D -flip flops of both level and edge triggered clock inputs are developed. Compared with the recently reported designs in the literature, it is observed that the quantum cost of the proposed D -flip flops is decreased by more than 28% with a cell count of 34, which in turn defines the low area too. Also, latency of the same is reduced by one-fourth with a value of 1. 2 5 × 1 0 − 1 2 s. As far as the sequence detector is concerned, it is smaller in size at 0.16 μ m2 than the existing sequential circuits with a reduction in area and quantum cost by 30%. Further, from the bit stream it detects, the proposed sequence detector can also be used as negative pulse detector and interrupt handler circuit in the future QCA-based digital systems to detect the external interrupts. [ABSTRACT FROM AUTHOR]

Quantum dot cellular automata (QCA) is an emerging transistor-less paradigm with high chip density, ultra-low power and high-speed computation capabilities. Due to programmable design approach, configurable architectures always draw the attention of researchers and manufacturers. Configurable structure has ability to change its functionality even after the product has been formed. This feature makes the circuit suitable for variety of applications. If the configurable circuit is high speed, power aware and nano-size, it drastically improves the performance of high-end complex circuits such as field-programmable gate array (FPGA). Configurable architectures are not much addressed in the QCA. This paper investigates the design and realization of a novel configurable logic module (CLM) in QCA framework. The proposed module is constructed using D flip flop, multiplexer and a programmable block (PB). This module is resilient owing to the efficient design of combinational as well as sequential circuits. The ability and flexibility of the proposed module are further showcased by implementing the high-level circuits such as 2 bit, 3 bit and 4-bit slice architectures for field-programmable gate array (FPGA). The proposed QCA-based 4-bit slice circuit has shown an improvement of 49.77% in cell count and 35.56% in area when compared with one of the equivalent existing circuits. The configurability of the proposed circuit is twofold. Firstly, FPGA itself is the programmable device, and secondly, the proposed module (CLM) which forms the base of FPGA is also programmable. Subsequently, the proposed configurable logic module can be effectively used for the future generation programmable logic devices. [ABSTRACT FROM AUTHOR]

The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY FSMs based on two methods of structural decomposition (the replacement of inputs and encoding of output collections). The main idea is to use two types of state codes for implementing systems of partial Boolean functions. Some functions are based on maximum binary codes; other functions depend on extended state codes. The reduction in LUT counts is based on using the method of twofold state assignment. The proposed method makes it possible to obtain FPGA-based FSM circuits with four logic levels. Only one LUT is required to implement the circuit corresponding to any partial function. An example of FSM synthesis using the proposed method is shown. The results of the conducted experiments show that the proposed approach produces LUT-based FSM circuits with better area-temporal characteristics than for circuits produced using such methods as Auto and One-hot of Vivado, JEDI, and MPY FSMs. Compared to MPY FSMs, the values of LUT counts are improved. On average, this improvement is 8.98%, but the gain reaches 13.65% for fairly complex FSMs. The maximum operating frequency is slightly improved as compared with the circuits of MPY FSMs (up to 0.64%). For both LUT counts and frequency, the gain increases together with the growth for the numbers of FSM inputs, outputs and states. [ABSTRACT FROM AUTHOR]