73 results on '"Sakui, K."'
Search Results
2. Investigating Japanese Learners' Beliefs About Language Learning.
3. A compact space and efficient drain current design for multipillar vertical MOSFETs
4. Investigating Japanese learners' beliefs about language learning
5. It's never too late: an overview of e-learning
6. The dark side of motivation: teachers' perspectives on 'unmotivation'
7. A new vertical MOSFET "Vertical Logic Circuit (VLC) MOSFET" suppressing asymmetric characteristics and realizing an ultra compact and robust logic circuit
8. A high efficient, low power, and compact charge pump by vertical MOSFET's
9. A Compact Space and Efficient Drain Current Design for Multi-Pillar Vertical MOSFET's
10. Wearing two pairs of shoes: language teaching in Japan
11. A unique and accurate extraction technique of the asymmetric bottom-pillar resistance for the vertical MOSFET.
12. Design impacts on NAND Flash memory core circuits with vertical MOSFETs.
13. A compact and low power logic design for multi-pillar vertical MOSFETs.
14. Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory
15. A source-line programming scheme for low-voltage operation NAND flash memories
16. A CMOS bandgap reference circuit with sub-1-V operation
17. A negative V/sub th/ cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories
18. A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology
19. Quick address detection of anomalous memory cells in a flash memory test structure
20. A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory
21. The effects of impact ionization on the operation of neighboring devices and circuits
22. Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND memory.
23. A 1.13um2 Memory Cell Technology for Reliable 3.3V 64M NAND EEPROMs
24. BiCMOS circuit technology for high-speed DRAMs
25. A 2.3 mu m/sup 2/ memory cell structure for 16 Mb NAND EEPROMs.
26. A reliable bi-polarity write/erase technology in flash EEPROMs.
27. An Active Substrate Mcm System.
28. A quick address detection of an anomalous memory cell for flash EEPROM.
29. A new static memory cell based on reverse base current (RBC) effect of bipolar transistor.
30. A new technique for measuring threshold voltage distribution in flash EEPROM devices.
31. Extended data retention characteristics after more than 10/sup 4/ write and erase cycles in EEPROMs.
32. Extended Data Retention Characteristics after More than 104 Write and Erase Cycles in Eeproms
33. A 130-mm2, 256-Mbit NAND flash with shallow trench isolation technology.
34. A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories.
35. Effect of intervalence-band interaction on relaxation time and transport coefficients for holes in non-polar semiconductors.
36. A 120-mm/sup 2/ 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed.
37. An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.
38. Noise-generation analysis and noise-suppression design techniques in megabit DRAMs.
39. A high-performance 1-Mbit dynamic RAM with a folded capacitor cell.
40. A new static memory cell based on the reverse base current effect of bipolar transistors.
41. Temperature dependence of mobility and Hall coefficient factor for holes of highly pure silicon
42. A reliable bi-polarity write/erase technology in flash EEPROMs
43. A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories
44. A sophisticated bit-by-bit verifying scheme for NAND EEPROMs
45. A CMOS band-gap reference circuit with sub 1 V operation
46. A 2.3 mu m/sup 2/ memory cell structure for 16 Mb NAND EEPROMs
47. Extended data retention characteristics after more than 10/sup 4/ write and erase cycles in EEPROMs
48. A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories
49. A new technique for measuring threshold voltage distribution in flash EEPROM devices
50. A compact, high-speed, and low-power design for multi-pillar vertical MOSFET's, suppressing characteristic influences by process fluctuation.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.