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In this paper, a novel frequency synchronization method is proposed for fast connection the islanded microgrid to the existing grid. In the conventional frequency synchronization method, the output of the synchronization controller is limited to maintain the voltage quality of the islanded microgrid. Due to this limitation of the output, the micro grid voltage has a nonlinear characteristic during the synchronization process. Conventional methods that do not consider the nonlinear characteristic have a drawback in that the synchronization speed can be slowed depending on the convergence direction of the frequency. To overcome the drawback, the nonlinear characteristic of the conventional method is analysed during the synchronization process. Based on the analysis, the synchronization speed is predicted according to the synchronization direction of the microgrid voltage. Using this prediction, a novel synchronization technique that finds a relatively fast synchronization direction is proposed. A 2MVA microgrid system is constructed using a real-time hardware-in-loop system and experimental results are presented to verify the validity of the proposed method. From experimental results, it is confirmed that the proposed method guarantees a faster synchronization speed than the conventional method.

Due to the rapid development of flash memory technology, NAND flash has been widely used as a storage device in portable embedded systems, personal computers, and enterprise systems. However, flash memory is prone to performance degradation due to the long latency in flash program operations and flash erasure operations. One common technique for hiding long program latency is to use a temporal buffer to hold write data. Although DRAM is often used to implement the buffer because of its high performance and low bit cost, it is volatile; thus, that the data may be lost on power failure in the storage system. As a solution to this issue, recent operating systems frequently issue flush commands to force storage devices to permanently move data from the buffer into the non-volatile area. However, the excessive use of flush commands may worsen the write performance of the storage systems. In this paper, we propose two data loss recovery techniques that require fewer write operations to flash memory. These techniques remove unnecessary flash writes by storing storage metadata along with user data simultaneously by utilizing the spare area associated with each data page.

컴퓨터의 그래픽 연산장치인 GPU는 그래픽 데이터의 연산뿐만 아니라 일반시스템 데이터를 처리할 수 있도록 발전되었으며, 3D 그래픽 관련 알고리즘이나 병렬 실행이 가능한 코드에 대해서는 CPU 보다 우수한 성능을 보여주고 있다. CPU 기반으로 제작된 일반적인 알고리즘을 GPU에서 실행하기 위해서는, GPU 시스템의 아키텍처를 이해하고 병렬처리 능력과 새로운 메모리 구조를 고려하여 코드를 재작성하여야 한다. 이를 위해서는 알고리즘을 성능 예측 모델에 적용하여 GPU 시스템에서 예상되는 성능 예측이 필수적이다. 이를 통해 GPU 기반 어플리케이션 개발에서 발생할 수 있는 문제점들을 사전에 예측하고, 성능에 대한 평가 지표를 구성할 수 있다. 본 논문에서는 AES 암호화 알고리즘에 성능예측 모델을 적용하여 작업량이 많은 조건하에서 높은 정확도로 성능 예측을 수행하였다.

NAND flash memory has been widely used as a storage medium in mobile devices, PCs, and workstations due to its advantages such as low power consumption, high performance, and random accessability compared to a hard disk drive. However, NAND flash cannot support in-place update so that it is mandatory to erase the entire block before overwriting the corresponding page. In order to overcome this drawback, flash storages need a software support, named Flash Translation Layer. However, as the high performance mass NAND flash memory is getting widely used, the size of mapping tables is increasing more than the limited DRAM size. In this paper, we propose an adaptive mapping information caching algorithm based on page mapping to solve this DRAM space shortage problem. Our algorithm uses a mapping information caching scheme which minimize the flash memory access frequency based on the analysis of several workloads. The experimental results show that the proposed algorithm can increase the performance by up to 70% comparing with the previous mapping information caching algorithm.

NAND flash memory is widely used in many embedded systems owing to such advantages as a small size, shock resistance, and low power consumption. However, NAND flash memory has certain hardware limitations such as an "erase-before-write" constraint, which creates a long write latency. Therefore, many studies have been performed to reduce the write latency of NAND flash, one of which uses phase-changed RAM (PRAM) as a supplemental device to overcome the disadvantages of NAND flash memory. However, it is difficult to apply PRAM to storage systems owing to its limited density and high cost per capacity. To solve this problem, a novel management scheme for PRAM/NAND flash hybrid storage is proposed. Our proposed method uses limited PRAM space more efficiently by reducing the size of the data to be stored through an efficient compression scheme using differential values and rates. In addition, the proposed method improves the performance and durability of storage systems by efficiently reducing the flash program operation. Our experiments show that the proposed scheme can improve the performance and durability of PRAM/NAND flash hybrid storage with only slight increases in hardware costs.

Recently, NAND flash memory has been widely adopted as a storage medium in various devices such as mobile phones, MP3 players, and digital cameras. In particular, Solid State Drives (SSDs), which are composed of multiple NAND flash memories, have gradually replaced hard disk drives (HDD). However, SSDs have an inherent weakness stemming from NAND flash memory and its complex architecture. This phenomenon makes it difficult to analyze and optimize the performance of SSD controllers. To overcome this weakness, highly accurate system simulations are needed for exploring architectural parameters to maximize the performance during the design phase. In this paper, we implement a simulator that considers all of the hardware components in SSD to assist in generating quantitatively accurate analysis when an algorithm or controller is realized. This simulator models the detailed characteristics of hardware components such as operation clock frequency and resource conflicts in order to represent SSD in great detail. In the experiments section, we verify the impacts of interface speed, page size, and other configuration parameters by using this cycle accurate simulator. These analysis results can then be used as raw data for optimization.

Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as a storage media in embedded and computer system environments. However, there are many shortcomings in flash memory such as potentially high I/O latency due to erase-before-write and poor durability due to limited erase cycles. To address these performance and reliability anomalies, many large-scale storage systems use redundancy-based parallel access schemes such as RAID techniques. However, such redundancy-based schemes incur high overhead due to generating and storing redundancy information, especially in flash-based storage systems. In this paper, we propose a novel and performance-effective approach using a redundancy-based data management scheme in flash storage, called Flash-aware Redundancy Array. The proposed technique not only reduces the redundancy management overhead by performing redundancy update operations during idle periods, but also provides a preventive mechanism to recover data from unexpected read errors occurring before such redundancy update operations finish. From the experiments, we found that the proposed technique improves flash-based storage systems by 19% in average execution time as compared to other redundancy-based approaches.

The popularity of NAND flash memory has been growing rapidly in recent years, but the SSD (Solid-State Disk) has shown limited success in its battle against the hard disk. Besides the high price, SSD suffers performance degradation under random write requests, due to the intrinsic weak points of NAND flash: erase-before-write, asymmetric read/write access time, and limited program/erase cycles. In order to overcome these drawbacks, many buffer replacement algorithms have been proposed. However, considering the cost of write operations, it would be beneficial to have dirty pages updated before being flushed to flash memory. In this paper, we propose a new buffer management scheme to retain write-intensive pages in the buffer, and we confirm its effectiveness by applying it to one of the existing buffer management schemes. The simulation results indicate that the proposed scheme reduces up to 30% of the write count, and, therefore, extends the lifetime of NAND flash memories.

NAND flash memory has attractive features compared to hard disk drives such as small size, no mechanical noise and shock resistance. But it also has some drawbacks such as no support for in-place updates and limited program/erase cycles, which trigger the development of sophisticated buffer management algorithms in order to reduce write and/or erase operations to flash memory. The significant gap in update frequency between hot and cold data motivates us to separate hot and cold data on different flash blocks to avoid unnecessary program/erase cycles. Many buffer management algorithms determine a request to be hot or cold based on its requested data size. However, the data size could become a wrong indicator of update frequency in many applications. In this paper, we propose a new hot/cold identification scheme in order to increase identification accuracy and, thus, to enhance storage performance and durability by reducing program/erase cycles. The proposed technique uses the process identification used in many operating systems as a hot/cold indicator. The experimental results show that the proposed scheme contributes to high performance and durability as compared to previously proposed identification schemes.

The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to idiosyncrasies such as non-volatility and low energy consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. In this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can decrease average response time by up to 4 times and increase durability by 4 times by adding only a small hardware cost.

Recently flash memory devices have been widely used in mobile storage systems. Users run various applications that require frequent access to data in the storage. However, the storage data access is usually handled through several software layers in host systems, and therefore the storage performance may be affected by individual software layers as well as sophisticated interaction between them. In this paper, we analyze the behavior of individual software layers involved in data access operations in a mobile device and find the layers that significantly contribute to performance degradation. The performance impact of IO schedulers in Android systems is also investigated.

In NAND flash storages, the invalidated pages could occupy the storage space until being erased. In order to preserve sustained write performance and storage capacity, the storage controller must eliminate these pages through garbage collection operations. However, the garbage collection operations may cause high computation overhead while selecting victim blocks, thereby resulting in the host system suffering from unendurable storage-access latency as well as performance degradation. In this paper, we propose an efficient garbage collection mechanism, which not only eliminates the computation overhead in victim block selection, but also improves responsiveness to the host requests by making the garbage collection operation preemptive.

MLC NAND flash memory has been widely used as a storage device in mobile and desktop computing systems. However, MLC NAND flash memory may cause a data loss problem because the LSB-page programmed data can be lost when a power failure occurs in the middle of a MSB-page program operation. In this paper, we propose a device-level voltage control scheme in order to overcome this problem. With the theoretical feasibility of our proposed scheme, the storage controller could fully restore the LSB-page programmed data at device-level after a power failure.

Memory manufacturers have recently advanced silicon technology to implement the multi-level cell technique onto NAND flash for the reduction of per-bit device cost. However, this technical improvement has introduced an additional problem of reliability and/or durability degradation, leading to the inevitable use of error detection and correction techniques. To increase the number of correctable error bit in recent flash memories, ECC techniques tend to use longer code bits. As the silicon technology of NAND device evolves, such growing code bits for a user data page could overflow its corresponding spare area in later devices. In this paper, we propose a novel management mechanism of excessively long error correction codes using user data area. The proposed mechanism is capable of providing error correction capability for highly error-prone NAND devices by efficiently managing long ECC codes only with negligible performance degradation.

This paper presents a hot/cold data identification technique for NAND flash storage systems. The proposed technique uses both compression ratio and sector size of requested data as identification criteria. In order to avoid high overhead due to compression process, the technique determines compression ratio using a fraction of data. The experimental results show that this technique contributes to effectively identify hot data and when used in buffer management to increase the hit rate effectively.

In NAND flash memory based storage systems, a flash translation layer (FTL) is usually employed to hide shortcomings of NAND flash memory such as erase-before-write and asymmetric read/write response time. Although there are several types of FTLs according to the mapping granularity, it is a recent trend to use a page-level mapping FTL. There are two basic methods of power loss recovery (PLR) schemes for page-level mapping FTL: per-page-unit method and the map block-unit method; however, these methods have shortcomings in term of the recovery time and the mapping information management overhead, respectively. In order to overcome disadvantages of PLR, thus, we propose a novel PLR, named accumulative backup of mapping information for power loss recovery (A-PLR), which provides a stable data recovery performance without any management overhead.

NAND flash memory has become popular in the consumer market while its success in main storage market is still limited. One of the reasons is that NAND flash suffers severe performance degradation under random write requests, and these requests are inevitable since the complexity of the applications is growing rapidly. One way to mitigate the problem is by applying DRAM as the buffer between host and NAND flash to absorb these requests, and numbers of buffer management schemes such as CFLRU and FARS had been proposed. However, these algorithms do not respect write intensive and long-term pages enough. In this paper, we propose a buffer replacement algorithm with a smart eviction list and a brand new eviction criterion that helps retaining the write intensive pages in the buffer in order to lower down the number of write request into NAND flash memory. Experiments show that SEPL outperforms other algorithms in the traces where random access is dominant.

Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage media in the embedded and computer system environments. In the case of reliability, however, there are many shortcomings in flash memory: potentially high I/O latency due to erase-before-write and poor durability due to limited erase cycles. To overcome these problems, a RAID technique borrowed from storage technology based on hard disks is employed. In the RAID technology, multi-bit burst failures in the page, block or device are easily detected and corrected so that the reliability can be significantly enhanced. However the existing RAID-5 scheme for the flash-based storage has delayed response time for parity updating. To overcome this problem, we propose a novel approach using a RAID technique in flash storage, called Flash-aware Redundancy Array. In this approach, parity updates are postponed so that they are not included in the critical path of read and write operations. Instead, they are scheduled for when the device becomes idle. For example, the proposed scheme shows a 19% improvement in the average write response time, compared to other approaches.

The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to properties such as non-volatility and low energy consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. In this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can increase performance by up to 4 times and durability by 4 times by adding only a small hardware cost.

In this paper, an explicit PID force control approach is presented for automatic steering control of an autonomous robotic heavy duty vehicle to avoid collision with guardrails. The desired distance is provided by an explicit PID controller based on a virtual force error. Simulation studies are performed for controlling a steering angle of the bicycle model of the robotic vehicle to maintain the virtual desired force and thus the desired offset from the guardrail. I. INTRODUCTION IGHWAY construction and maintenance is a challenging and relatively unstructured environment, with many

This study proposes a compact broadband 180° Wilkinson divider which is composed of rightand lefthanded (RH-LH) transmission lines and an additional λ/2 transmission line to realise a 180° phase difference. In order to reduce the circuit size while maintaining the required broad band performance, all the transmission lines with positive or negative electrical lengths in the sub-compact 180° Wilkinson divider are realised by means of double-sectioned structures using π-type lumped passive networks, except for the λ/2 transmission line. The compact divider has a lumped passive realisation, even for the λ/2 transmission line in order to further reduce the size. The measured bandwidths of the conventional 180° Wilkinson divider, the conventional 180° Wilkinson divider using LH transmission lines, the semi-compact divider and the proposed compact divider, for the given specifications of 1 dB loss, 0.5 dB magnitude difference and 10° phase imbalance between the two output ports, are 240 MHz, 840 MHz, 1.06 GHz and 950 MHz, respectively. The proposed compact divider has a 89.2% reduction in the circuit size, compared to the conventional 180° Wilkinson divider.