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High-Pb solders have been used as die-attach and interconnect materials since long time for discrete power packages, including MOSFET, smart power ASICs, IGBT modules and integrated power modules, operating under high-power and high-current operation environments. Due to the known harmful effects of Pb to human health and the environment, alternative Pb-free solders and other Pb-free solutions have been studied for decades. But, Pb-free alternatives to replace high-lead solders are still in the infant age and no recognized drop-in solution is available yet. The exemption of using high-Pb solders has been extended again to 2021. iNEMI initiated a project and conducted an industry-wide survey to benchmark the availability of Pb-free die bonding materials, the technological feasibility for the same and the ongoing industrial trend. Based on the survey results, this paper presents the insights on the industrial preferences and the potential lead-free materials.

In past studies [1], it was established that board level reliability of the packages depends mainly upon the design of the package and the soldering technology used for mounting the components. There are many methods [2] to test the reliability, such as temperature cycling test, bend test, power cycling, etc. which have been studied and practiced. We need to consider the failure rate and failure mechanism both, to understand how specific loading conditions affect the failure of an assembly. In this study, PCB's with variable layer thicknesses and QFN package mountings are subjected to drop test. The packages are custom made with probable high density end application. It has been observed previously that the failure initiates at the solder joints in the form of cracks. Also, the solder joints fail at two particular regions [6]. Hence, the drop test simulation is carried out using ANSYS workbench with detailing of the solder joints. The forcing function is dependent on the acceleration of the drop and not on the height of the drop for this particular study. The stress resulting due to impact is analyzed and the possible impact life prediction models are suggested based on it. The results give the idea about stress concentration and the amount of deflection of the board. To understand the effect of variable thickness of the board layers on the reliability of the package, the thickness of individual layers is varied. As the core of the PCB needs to be constant in terms of material and composition, the thickness of only the outermost layers is altered. Each assembly with different thickness of the PCB layers was tested and analyzed for failure. The study gives an insight on the reliability of the QFN packages under impact loading and ways to improve the reliability of the solder joints.

Wafer Level Chip Scale packages use packaging technology at the wafer level instead of traditional method of assembling individual devices in packages. WCSP boards are being extensively used in handheld devices due to its smaller form factor, low cost and high packaging efficiency. WCSP has a relatively short solder life compared to other packages and so the reliability of these packages are of great concern. A PCB is a multi-layered structure in which each layer has different material characteristics and has a significant effect on the board itself. Removal of layers or changing the composition of the layers affects the solder balls' life [1], thus impacting the solder joint reliability of the boards. One of the key parameters in board level reliability is thermal cycling and during thermal cycling, stress is accumulated in the solders due to warpage of the board caused by coefficient of thermal expansion (CTE) and modulus mismatch between the layers [2–3]. This paper will try to address the possible effect of individual layers during thermal cycling by considering layer removal and by considering boards with different thickness created.