27 results on '"Schuddinck, Pieter"'
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2. CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark
3. Cost analysis of device options and scaling boosters below the A14 technology node
4. DTCO of sequential and monolithic CFET SRAM
5. Design-technology co-optimization overview of CFET architecture
6. CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling
7. Memories for NTC
8. Evaluation of BEOL scaling boosters for sub-2nm using enhanced-RO analysis
9. Design enablement of CFET devices for sub-2nm CMOS nodes
10. The Complementary FET (CFET) 6T-SRAM
11. DTCO of sequential and monolithic CFET SRAM
12. A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node
13. Two-level MOL and VHV routing style to enable extreme height scaling beyond 2nm technology node
14. Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm
15. Ge Devices: A Potential Candidate for Sub-5-nm Nodes?
16. Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI
17. Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm
18. Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7
19. Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node
20. Dedicated technology threshold voltage tuning for 6T SRAM beyond N7
21. DTCO of sequential and monolithic CFET SRAM.
22. Architectural strategies in standard-cell design for the 7 nm and beyond technology node
23. Post place and route design-technology co-optimization for scaling at single-digit nodes with constant ground rules.
24. DTCO at N7 and beyond: patterning and electrical compromises and opportunities
25. Vertical GAAFETs for the Ultimate CMOS Scaling.
26. DTCO at N7 and beyond: patterning and electrical compromises and opportunities
27. Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm.
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