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Electrical properties of two-dimensional and three-dimensional SrBi2Ta2O9 (SBT)-based ferroelectric capacitors are compared after integration. Ferroelectric contribution of the sidewall SBT in three-dimensional configuration is revealed to be strongly dependent on the Bi segregation occurring in the sidewall region during metal-organic chemical-vapor deposition (MOCVD) of the SBT layer.

Ferroelectric random access memory (FeRAM) is an attractive candidate technology for embedded nonvolatile memory, especially in applications where low power and high program speed are important. Market introduction of high-density FeRAM is, however, lagging behind standard complementary metal-oxide semiconductor (CMOS) because of the difficult integration technology. This paper discusses the major integration issues for high-density FeRAM, based on SrBi2Ta2O9 (strontium bismuth tantalate or SBT), in relation to the fabrication of our stacked cell structure. We have worked in the previous years on the development of SBT-FeRAM integration technology, based on a so-called pseudo-three-dimensional (3D) cell, with a capacitor that can be scaled from quasi two-dimensional towards a true three-dimensional capacitor where the sidewalls will importantly contribute to the signal. In the first phase of our integration development, we integrated our FeRAM cell in a 0.35 μm CMOS technology. In a second phase, then, possibility of scaling of our cell is demonstrated in 0.18 μm technology. The excellent electrical and reliability properties of the small integrated ferroelectric capacitors prove the feasibility of the technology, while the verification of the potential 3D effect confirms the basic scaling potential of our concept beyond that of the single-mask capacitor. The paper outlines the different material and technological challenges, and working solutions are demonstrated. While some issues are specific to our own cell, many are applicable to different stacked FeRAM cell concepts, or will become more general concerns when more developments are moving into 3D structures. [ABSTRACT FROM AUTHOR]

The difficult scaling of ferroelectric random access memories with the complementary metal-oxide semiconductor technology roadmap requires integration of three-dimensional (3D) ferroelectric capacitors (FeCAP’s). In this work the unusual electrical behavior of 3D FeCAP sidewalls was studied by comparing the electrical properties of two-dimensional and 3D integrated FeCAP structures. We evidenced composition variations of the SrBi2Ta2O9 (SBT) film in the sidewalls with marked bismuth segregation during metal-organic chemical-vapor deposition (MOCVD) of the SBT film. The segregation was reduced after decreasing the deposition temperature from 440 °C, whereby the Bi-rich phase in the sidewalls does not contribute to polarization, down to 405 °C, whereby sidewall SBT contributes to polarization. After further optimization of the MOCVD conditions at 405 °C, the segregation is minimized and the ferroelectric contribution of the sidewall SBT is almost the same as the contribution of the planar SBT. As a result, 3D FeCAP’s integrated up to metal interconnection exhibit a remnant polarization Pr∼7.5 μC/cm2. [ABSTRACT FROM AUTHOR]

Different aspects of the integration of strontium bismuth tantalate (SBT)-based high-density ferroelectric random access memory (FeRAM) is discussed in relation to the fabrication of pseudo-three-dimensional (3D) cell structure. The excellent electrical and reliability properties of the small integrated FeCAP prove the feasibility of the technology, while the verification of the potential electrical 3D effect confirms the basic scaling potential of the concept beyond that of the single-mask capacitor.

This paper reports on the integration of MOCVD SBT based stacked ferroelectric capacitors in a 0.35 μm CMOS technology for embedded FeRAM, using a ferroelectric capacitor (FeCap) that is scalable to a 3D configuration. The electrical parameters of the CMOS devices with and without FeCap integration are presented. No significant shifts of the CMOS characteristics are noticed after FeCap integration. Also the effects of the CMOS processing on the FeCaps are discussed. There is no degradation of the hysteresis loops of the FeCaps throughout the CMOS back-end-of-line processing, which proves that the integrated encapsulation layer effectively prevents any hydrogen induced damage. Another key element in the successful integration of stacked ferroelectric devices is the conductive oxygen barrier, which protects the plugs from oxidation. A low contact resistance and a high yield are obtained on plug contacts covered by the oxygen barrier. Also damage free etching is a critical issue in FeRAM integration. Excellent results are presented for the etch process to form the contacts to the electrodes. [ABSTRACT FROM AUTHOR]

Using high-quality polycrystalline chemical-vapor-deposited diamond films with large grains (∼ 100 μm), field effect transistors (FETs) with gate lengths of 0.1 μm were fabricated. From the RF characteristics, the maximum transition frequency ƒT and the maximum frequency of oscillation ƒmax were ∼ 45 and ∼ 120 GHz, respectively. The ƒT and ƒmax values are much higher than the highest values for single-crystalline diamond FETs. The dc characteristics of the FET showed a drain-current density IDS of 550 mA/mm at gate-source voltage VGS of -3.5 V and a maximum transconductance gm of 143 mS/mm at drain voltage VDS of -8 V. These results indicate that the high-quality polycrystalline diamond film, whose maximum size is 4 in at present, is a most promising substrate for diamond electronic devices. [ABSTRACT FROM AUTHOR]

As compared to usual planar capacitors, three-dimensional (3D) ferroelectric capacitors display a large polarization increase due to the additional electrical contribution of the capacitor sidewalls. However, in 3D capacitors the polarization increase with respect to the planar geometry is lower than expected. To uncover the origin of this discrepancy, the microstructure of 3D Sr0.8Bi2.2Ta2O9-based (SBT) capacitors was studied. First, high-resolution synchrotron x-ray diffraction has found a unit cell expansion of the SBT phase in the capacitor sidewalls. From local chemical analyses, this lattice distortion has been correlated to composition variations in this region. These microstructural changes are due to the peculiar topography of the etched bottom electrode and to the variety of layers in contact with the SBT film, which can explain the nonoptimized polarization in 3D capacitors. [ABSTRACT FROM AUTHOR]

We compare the results of ab initio calculations with measured reflection anisotropy spectra and show that strongly bound surface-state excitons occur on the clean diamond (100) surface. These excitons are found to have a binding energy close to 1 eV, the strongest ever observed at a semiconductor surface. Important electron-hole interaction effects on the line shape of the optical transitions above the surface-state gap are also found.