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Materials technology co-optimization (MTCO) modeling is used for the first time to simulate Performance-Power-Area (PPA) benefits of self-aligned gate contact (SAGC) technology. We also demonstrate a process flow to integrate novel CMOS compatible materials and processes to enable SAGC at the 3nm node and below.

Program/Erase (P/E) cycling endurance in poly-Si/Al(2)O(3)/SiN/SiO(2)/Si (SANOS) memories is systematically studied. Cycling-induced trap generation, memory window (MW) closure, and eventual stack breakdown are shown to be strongly influenced by the material composition of the silicon nitride (SiN) charge trap layer. P/E pulsewidth and amplitude, as well as starting program and erase flatband voltage (V(FB)) levels (therefore the overall MW), are shown to uniquely impact stack degradation and breakdown. An electron-flux-driven anode hole generation model is proposed, and trap generation in both SiN and tunnel oxide are used to explain stack degradation and breakdown. This paper emphasizes the importance of SiN layer optimization for reliably sustaining large MW during P/E operation of SANOS memories.

Composition of the silicon-nitride charge trap layer strongly impacts electron and hole trap properties. This significantly impacts charge trap flash memory performance and reliability. Important trade-offs between Program/Erase (P/E) levels (memory window) and retention loss is shown and critical trends identified. Increasing the Si-richness of the SiN layer improves memory window by increasing erase efficiency. E-state retention characteristics are improved but at the expense of higher P-state retention loss.

Silicon-nitride trap layer stoichiometry in charge trap flash (CTF) memory strongly impacts electron and hole trap properties, memory performance, and reliability. Important tradeoffs between program/erase (P/E) levels (memory window), P- and E-state retention loss, and E-state window closure during cycling are shown. Increasing the Si richness of the SiN layer improves memory window, cycling endurance, and E-state retention loss but at the cost of higher P-state retention loss. The choice of SiN stoichiometry to optimize CTF memory performance and reliability is discussed.

Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap Flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N(+)) to Si-rich (Si(+)) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant over-erase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si(+) SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si(+) SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND Flash applications.

The effect of nitride composition, i.e. Si-rich (Si+) and N-rich (N+) nitride bi-layers separated by an oxynitride (SiON) layer on memory performance and reliability is studied. Bottom Si+ layer and top N+ forms the Si+/N+ bi-layer that is compared to the opposite configuration of N+/Si+ bi-layer to reveal large impact on memory performance and reliability. Si+/N+ bi-layers exhibit superior P/E windows and endurance characteristics but worse retention charge loss compared to N+/Si+ stacks. The oxynitride layer composition and position play a dominant role in trap generation as evident from endurance performance. A low energy-threshold degradation mechanism with higher degradation of the SiON layer with greater H-content is observed. A Si-H bond breaking mechanism is proposed as trap generation mechanism during endurance cycling. Retention is primarily bottom nitride composition dependent as tunnel oxide is shown to be the dominant charge loss path.

State-of-the-art low-K spacer technology featuring novel CVD-SiBCN material is demonstrated for the first time. A significant 20% CMOS ring speed enhancement is demonstrated with SiBCN (K=5.2) spacer, compared to Si3N4 (K=7.5) spacer, due to reduced fringing capacitance and enhanced strain effects by spacer-PSS and CESL techniques. Electron mobility is improved by 6% for long channel NMOS transistor and gm,max is increased by 11% for short 35 nm physical gate length NMOS using a preferable spacer structure that is comprised of a low stress SiBCN spacer on thin SiO2 liner and a final 600degC rapid thermal post-anneal. Superior GIDL and better gate leakage is obtained because low permittivity SiBCN alleviates gate-fringing field effects (GF effects), and device reliability is not adversely impacted by this new process.

The performance and reliability of charge trap flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied. Single layer devices show lower memory window and poor cycling endurance, and the underlying physical mechanisms for these issues are explained. An engineered trap layer consisting of Si-rich and N-rich nitride interfaced by a SiON barrier layer is proposed. The effect of varying the SiON interfacial layer position on memory window and reliability is investigated. Optimum bi-layer device shows higher memory window and negligible degradation due to cycling (at higher memory window) compared to single layer films. The role of SiON interface in improving the performance and reliability of bi-layer stacks is explained.

Less than 10% pattern-dependent microloading and greater than 95% step coverage are required for low temperature deposition of Si3N4 spacer and etch stop films in advanced logic and dynamic random access memory semiconductor applications. A single-wafer chemical vapor deposition chamber was utilized to analyze pattern loading effect on 130 nm and 90 nm patterned wafers. With silane-ammonia chemistry as the focus, a variety of processing methods were employed utilizing continuous and cyclical deposition modes. In addition, methods to modify diffusion and/or reaction rates were studied, such as remote plasma excitation and carrier gas modifications. Finally, chemistry-related variables were evaluated by changing the Si-source precursor. It was concluded that process chemistry and specifically precursor is the most dominant factor determining pattern loading effect.

Sub-90 nm device design presents challenges for lowering thermal budget as well as depositing uniform and conformal thin films for front-end-of-line silicon nitride applications. Among other low-temperature precursors forsilicon nitride film deposition, bis(tertiary-butylamino)silane (BTBAS) has gained acceptance for critical applications such as spacer. This paper describes BTBAS based silicon nitride film deposition process optimization for spacer and etch stop applications. The single-wafer chamber design can control and tune the film with respect to deposition rate, film composition, wet etch rate, and film mechanical stress by adjustment of process conditions such as temperature, pressure, and gas flow rates. Computational flow and thermal simulations are employed to optimize chamber design to achieve uniform thin films.