Search

We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out from RO environments. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.

In this paper we demonstrate a novel methodology to electrically test and characterize resistive random-access memory (RRAM) single bit devices for deep learning application. We extract critical device performance metrics for validating and optimizing fabrication processes which feed into yield learning. We adopt the algorithm-based bias condition search methodology and extract forming and switching voltage parameters without overdriving the devices. This test methodology can be used for Technology Development Learning Cycle in a research and development environment.

Ring Oscillators (ROs) are used for yield learning during the research phase of a CMO technology. We performed cross-sections and showed that the open and short defects are in the middle of line (MOL) gate structures. The defects which are related to MOL or prior processes, as well as the design and density, will be discussed in the paper.

Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a factor of two improvement in comparison to optical or scanning electron microscope based processes. This paper provides an additional update on this project. The study is about a GDS based process developed to simplify the complicated workflow for examining discrete electrical failures. The results of this study indicated that the recipe prototype developed on a test structure had a unique feature that consisted of an approximately 45nm by 200nm Cu line segment. Executing the prototype recipe on a wafer at the same process point fabricated 6 months after the original wafer yielded four identical successful samples of about 30nm sample thickness. This technique can thus be extended to large 2D arrays of small structures.

Historically, haze metrology on KLA-Tencor Surfscan® unpatterned wafer inspection systems is the preferred inline non-destructive method for ascertaining crystal quality of epitaxial deposited films. However, this metrology is limited to unpatterned blanket wafers. This paper describes a non- destructive inline optical methodology for measuring epitaxial quality of both blanket and patterned wafers using a novel fast turnaround machine learning method that can be applied to patterned and unpatterned substrates by utilizing the background noise obtained during broadband plasma optical defect inspection. This machine learning method is an innovative nuisance filtering algorithm used in inline defect inspection tools, named iDO™ 2.0 (inLine Defect Organizer™). The study showed a promising machine learning approach that repeatably measures low and high defect densities which are consistent with Secco etch data.

Ring oscillators (ROs) are used for yield learning during the research phase of a CMOS technology generation. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.

Self-aligned contact (SAC) is required for 7 nm node to reduce susceptibility of contact-to-gate short failures. This requires forming a SAC cap on metal-recessed gate. The SAC cap formation is usually achieved by removing nitride on the field by planarization techniques such CMP (chemical mechanical polishing) or GCIB (gas cluster ion beam) processes. Significant gate stack height variation can be observed lot-to-lot and wafer-to-wafer due to accumulated variations from multiple steps, including several CMP steps, before the SAC cap module, especially during early research and development prior to full optimization of the steps before the SAC cap module. GCIB potentially offers a method by which the early development stage variation due to CMP steps can be reduced, allowing integration and device learning during the early stages of a program. This study shows a comparison of SAC cap formation by CMP only vs. GCIB with integrated metrology enabled location specific processing. By using GCIB with feed-forward scatterometry measurements taken from a 2D measurement pad we have been able to significantly improve both lot-to-lot and wafer-to-wafer variation on early development wafers. This has led to improvement in within wafer SAC cap thickness non-uniformity, wafer to wafer and lot to lot device yield for gate-contact over a CMP-only process flow.

This study investigates and demonstrates the enhancement in thermoelectric power factor for n-type AlZnO/InAlZnO multilayer quantum wells as compared to their counterpart bulk films. A 10–20% improvement is observed for operating temperatures

This study investigates the thermoelectric (TE) power factor for radiofrequency (RF)-sputtered n-type ZnO:Al/ZnO:(Al,In) multilayer quantum wells (QW) and the dependence on band-gap offset at high operating temperatures. The structures are 50 periods of 10-nm-thick barrier and well layers. The TE power factors for all films are promising (>20 × 10−4 W/m2 K); however, a decline in electronic transport is evident for each of the doped wells over a specific range of operating temperatures. This supports the need for optimum doping levels for a specific operating temperature range; e.g., 2 at.%, 5 at.%, and 8 at.% indium are optimum at 300 K to 600 K, 600 K to 725 K, and >725 K, respectively. A model has also been developed to calculate the QW electronic transport as a function of temperature and band-gap offset, which is subsequently related to doping concentration. This model confirms a loss in electrical conductivity due to charge carriers gaining enough kinetic energy to overcome the QW barrier, which results in multilayer hopping across well–barrier interfaces. In addition, film microstructure and interface roughness have been determined by x-ray and spectroscopy techniques.

An improvement in the thermoelectric power factor of Al doped ZnO has been achieved by means of co-doping with indium using a dual magnetron sputtering system. The concentration of indium in the film was varied from 0 to 10 atomic % by varying the RF power of the In target, with the ZnO:Al target fixed at 100 W. It has been found that the films with In concentrations at or below 5 at.% have no significant change in microstructure, and yet a marked improvement in thermopower. At higher doping levels, the Seebeck coefficient continues to increase, however poly-crystallinity is induced in the ZnO matrix which results in a considerable decrease in electrical conductivity. This factor ultimately has a negative impact on the materials power factor. Taking into account the films studied, (ZnO)Al.03In.02 exhibited the best thermoelectric properties with an electrical conductivity of 5.88 × 102 S/cm and a Seebeck coefficient of −220 μV/K at 975 K, resulting in a power factor is 22.1 × 10−4 Wm−1 K−2, which is three times greater than for the film with no In doping. Film microstructure, composition, and thermal stability were investigated using X-ray diffraction, scanning electron microscopy, and Auger electron spectroscopy.

We report FDSOI devices with a 20nm gate length (L G ) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V dd of 0.75V, competitive effective current (I eff ) reaches 550/340 µA/µm for NFET, at I off of 100/1 nA/µm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V dd of 0.75V, PFET I eff reaches 495/260 µA/µm, at I off of 100/1 nA/µm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.

For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record high speed ring oscillator (fan-out = 3) with delay of 8.5 ps/stage and 11.2 ps/stage at V DD = 0.9V and V DD = 0.7V, respectively, outperforming state-of-the-art finFET results. A novel “STI-last” integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths. Furthermore, cSiGe modulates device V t , thus providing an additional knob to enable multi-V t while maintaining undoped channels for all devices.

Formation of heavy C and/or P doping Si alloy with a strain and/or low resistivity in FinFET S/D having only {110} plane on fin sidewall poses a challenge because, if the CVD selective epitaxy typically used in recent S/D process integration is employed, it is extremely difficult to grow heavily doped Si alloys with defect-free microstructure on {110} crystallographic plane. We propose the combination of cryogenic ion-implant amorphization followed by nonmelt laser annealing regrowth for both strained C-incorporated Si solid-phase epitaxy and improvement of P-activation in heavily P-doped Si alloy epitaxially grown film, while annihilating defects. In this paper, the diffusion and the activation of C atoms and P atoms in Si with C additive are investigated for different nonmelt laser annealing conditions. Additionally, the influence of cryogenic implantation of Si+ into amorphized P-doped Si epitaxial layer followed by nonmelt laser annealing recystallization on the diffusion and activation of P atoms in Si is discussed.