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5 results on '"Sebai, Farid"'

1. Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Author

Gupta, Anshul, primary, Pedreira, Olalla Varela, additional, Arutchelvan, Goutham, additional, Zahedmanesh, Houman, additional, Devriendt, Katia, additional, Mertens, Hans, additional, Tao, Zheng, additional, Ritzenthaler, Romain, additional, Wang, Shouhua, additional, Radisic, Dunja, additional, Kenis, Karine, additional, Teugels, Lieve, additional, Sebai, Farid, additional, Lorant, Christophe, additional, Jourdan, Nicolas, additional, Chan, Boon Teik, additional, Subramanian, Sujith, additional, Schleicher, Filip, additional, Hopf, Toby, additional, Peter, Antony Premkumar, additional, Rassoul, Nouredine, additional, Debruyn, Haroen, additional, Demonie, Ingrid, additional, Siew, Yong Kong, additional, Chiarella, Thomas, additional, Briggs, Basoene, additional, Zhou, Xiuju, additional, Rosseel, Erik, additional, De Keersgieter, An, additional, Capogreco, Elena, additional, Litta, Eugenio Dentoni, additional, Boccardi, Guillaume, additional, Baudot, Sylvain, additional, Mannaert, Geert, additional, Bontemps, Noemie, additional, Sepulveda, A., additional, Mertens, Sofie, additional, Kim, Min-Soo, additional, Dupuy, Emmanuel, additional, Vandersmissen, Kevin, additional, Paolillo, Sara, additional, Yakimets, Dmitry, additional, Chehab, Bilal, additional, Favia, Paola, additional, Drijbooms, Christel, additional, Cousserier, Joris, additional, Jaysankar, Manoj, additional, Lazzarino, Frederic, additional, Morin, Pierre, additional, Altamirano, Efrain, additional, Mitard, Jerome, additional, Wilson, Christopher J., additional, Holsteyns, Frank, additional, Boemmels, Juergen, additional, Demuynck, Steven, additional, Tokei, Zsolt, additional, and Horiguchi, Naoto, additional

Published
2020
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2. Cleaning and Strip Requirement for Metal Gate Based CMOS Integration

Author

Martine Cleas, Johan Albert, E. Rohr, Tom Schram, S. Kubicek, Masayuki Wada, Rita Vos, and Sebai Farid

Subjects
Focus (computing), CMOS, Hardware_GENERAL, Computer science, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Process (computing), Hardware_PERFORMANCEANDRELIABILITY, Dielectric, Metal gate, Hardware_LOGICDESIGN, Dual (category theory)
Abstract

This paper describes the basic process steps involved in the dual metal gate CMOS integration. It focuses on the differences between a dual metal dual dielectric and single metal dual dielectric integration. The focus is on basic process steps involved in both process flows, but device data are also presented to illustrate the processes.

Published
2009

4. A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond.

Author

Ritzenthaler, Romain, Schram, Tom, Spessot, Alessio, Caillat, Christian, Aoulaiche, Marc, Cho, Moon Ju, Noh, Kyoung Bong, Son, Yunik, Na, Hoon Joo, Kauerauf, Thomas, Douhard, Bastien, Nazir, Aftab, Chew, Soon Aik, Milenin, Alexey P., Altamirano-Sanchez, Efrain, Schoofs, Geert, Albert, Johan, Sebai, Farid, Vecchio, Emma, and Paraschiv, Vasile

Subjects
COMPLEMENTARY metal oxide semiconductors, DYNAMIC random access memory, STRAY currents, LOGIC circuits, METAL oxide semiconductor field-effect transistors, THERMAL stability
Abstract

In this paper, a low-cost and low-leakage gate-first high- \(k\) metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 \(\mu \) A/ \(\mu \) m can be obtained for an OFF-state current of \(10^{-10}\) A/ \(\mu \) m, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability. [ABSTRACT FROM AUTHOR]

Published
2014
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5. Poly-Silicon Etch with Diluted Ammonia: Application to Replacement Gate Integration Scheme

Author

Sebai, Farid, Del Agua Borniquel, Jose Ignacio, Vos, Rita, Absil, Philippe, Chiarella, Thomas, Vrancken, Christa, Boelen, Pieter, and Baiya, Evans

Abstract

With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].

Published
2009
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