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Wide voltage range operation for DSPs brings more versatility to achieve high energy efficiency in mobile applications. This paper describes a 32 bits DSP fabricated in 28 nm Ultra Thin Body and Box FDSOI technology. Body Biasing Voltage (VBB) scaling from 0 V up to ±2 V decreases the core VDDMIN to 397 mV and increases clock frequency by +400%@500 mV and +114%@1.3 V. The DSP frequency measurements show 2.6 GHz@1.3 V(VDD)@2 V(VBB) and 460 MHz@397 mV(VDD)@2 V(VBB). The lowest peak energy efficiency is measured at 62 pJ/op at 0.53 V. In addition to technological gains, maximum frequency tracking design techniques are proposed for wide voltage range operation. On silicon, at 0.6 V, those techniques allow high energy gain of 40.6% w.r.t. a worst case corner approach.

In this paper, the minimum operating voltage of master-slave flip-flops made in advanced fully-depleted silicon on insulator (FDSOI) technology, is studied through silicon measurements. A shift register of 1024 master-slave flip-flops has been fabricated in 28nm FDSOI technology in order to study the minimum operating voltage with respect to a wide back bias range allowed by the FDSOI technology. We show that a maximum yield is obtained for an optimum back bias couple (VBP for PMOS, VBN for NMOS) resulting from a tradeoff between speed and currents ratios. Results are given for a chain of 1, 16, 128, and 1024 FFs in series as well as for two different temperatures (30C and 80C). The minimum operating voltage of 1024 FFs is 230mV at 30C for a back biasing of (VBP,VBN) = (-0.5V,0.5V) and 299mV at 80C with (VBP,VBN) = (0V,0V).

Wide-voltage-range-operation DSPs bring more versatility to achieve high energy efficiency in mobile applications to increase signal processing complexity and handle a large range of performance specifications. This paper describes a 32b DSP fabricated in 28nm UTBB FDSOI technology [1]. Body-bias-voltage (VBB) scaling from 0V up to ±2V (Pwell/Nwell) decreases the DSP core VDDMIN to 397mV and increases clock frequency by +400% at 500mV and +114% at 1.3V. In addition to technology gains, dedicated design features are included to increase frequency over the full VDD range, considering parameter variations. As depicted in Fig. 27.1.1, the 32b datapath VLIW DSP is organized around a MAC dedicated to complex arithmetic and two dedicated operators: a cordic/divider and a compare/select. Data enters the circuit through a serial interface and code is run from a 64×32b register file. It has been shown in [1] that a given operating frequency can be achieved at a lower VDD in UTBB FDSOI compared to bulk by applying a forward-body bias. An additional design step is achieved in this work by (1) increasing the frequency at low VDD thanks to a specific selection and design of standard cells with respect to power vs. performance and (2) dynamically tracking the maximum frequency to cope with variations.

So far, pulse-triggered flip-flops (pulsed-FFs) are mainly used in high-performance digital circuits, thanks to their small data-to-output delay. However, they suffer from a poor robustness to local variations occurring at ultra-low-voltage (ULV). Thanks to an innovative pulse generator, the operability of an energy-efficient pulsed-FF was validated at ultra-low operating supply voltage. Measurements of delays and correct functionality are performed in 28nm FDSOI technology. Then, the effect of back bias voltage, a key point in FDSOI technology, is studied and it is shown that our pulsed-FF reaches a minimum operating supply voltage of 170mV.

In this paper, a robust and energy efficient pulse generator (PG), dedicated to pulse-triggered flip-flops (pulsed-FFs) in ultra-wide voltage range (UWVR) applications, is proposed. Pulsed-FFs are promising candidate for high-speed and low-power applications, thanks to their small data-to-output delay and their shareable PG. However, UWVR circuits work most of the time under the threshold voltage, where local variations lead to a huge spread in logic delays. Therefore, the designers have to ensure that the minimum width of the pulse signal activating the pulsed-FF is large enough to guarantee the correct functionality of the FF. On the other hand, a too large pulse window would lead to an increase of the hold time, and thus energy overhead for inserting delay buffers, which is not acceptable in energy-efficient circuits. This work presents a pulse generator exhibiting excellent performances in the three figures of merit of PGs. Postlayout simulations showed that, for a small area penalty, the robustness of the pulsed-FF is greatly improved.

The vision of the Internet-of-Things (IoT) calls for the deployment of trillions of wireless sensor nodes (WSNs) in our environment. A sustainable deployment of such a large number of electronic systems needs to be addressed with a Design-for-the-Environment approach. This requires minimizing 1) the embodied energy and carbon footprint of the WSN production, 2) the ecotoxicity of the WSN e-waste, and 3) the Internet traffic associated to the generated data. In this paper, we study how ultra-low-power yet high-performance systems-on-a-chip (SoCs) in nanometer CMOS technologies can contribute to these objectives by allowing compact batteryless WSNs with on-node data processing. We then review latest results achieved at the Universite catholique de Louvain in the field of green SoC design for a massive yet sustainable deployment of the IoT.

In this paper, a new metric to compute the setup time of pulse-triggered flip-flops (pulsed-FFs) is proposed. With the emergence of new technologies, digital circuits are pushing towards high-speed and energy efficient modes. Setup time is an essential aspect of the timing constraints of a synchronous digital circuit. It is a key parameter to determine the minimum clock cycle, which gives the timing and energy performances of circuits. Due to their small input-to-output delay (D-to-Q), pulsed-FFs are key candidate to be the determinant sequential cell of high-speed but also energy efficient circuits. This paper shows that, for pulsed-FFs, the conventional setup time metric based on minimum data-to-output delay is loosely extracted during automatic standard-cell characterization. Thereby, we propose a new metric for characterizing the setup time of pulsed-FFs based on the output transition time. Quantitative and qualitative advantages of the proposed metric are validated with SPICE simulations in 28nm fully-depleted silicon on insulator (FDSOI) technology. The obtained gain motivates a potential integration into standard-cell characterization tools.

The pre-silicon 22/20nm LSTP models we generated are available on-line1 and can be used for fair bulk vs. FD SOI benchmarks. The proposed modeling methodology unified for bulk and FD SOI can further be used to generate models for LOP process flavor and/or 16nm CMOS node.

This paper overviews the work done jointly during the European ENHANCE Project by the Remote Collaborative Working Methods (COSITE) and Human Factors (HF) tasks. The aim of COSITE was to put in place effective methods for remote collaborative work. It is clear that the elaboration of these methods is tightly concerned with human factors aspects. A scenario based on a real-time distributed collaborative environment was used to analyze the situation awareness perceived by users. The findings permit to understand the communication process and to generate best practices for using communication media.