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Photon absorption statistics combined with a simple model of resist chemistry triggered by each absorbed photon leads to a family of stochastic models with a Gaussian Random Field deprotection. Two important aspects of such models are discussed. First, the generalizations to stochastic reaction-diffusion models, accounting for the effects of depletion, and to models accounting for both exposure-resist stochastic and other process parameter variations, are presented. Second, several options for the stochastic metrics of EUVL processes, both meaningful and useful for lithographers and fast enough to be applicable to the full chip OPC and verification, are described, and some details of their implementations for the full-chip OPC verification and the results of tests are presented. The relation of one of the introduced stochastic metrics to the stochastic-caused variability of the electrical conductance of vertical interconnects (vias) is explained.

Generating curvilinear mask shapes in OPC instead of pure rectangular shapes is becoming more and more realistic as a method for improving wafer lithography performance. The main benefit of using curvilinear shapes is an improved process window, meaning that the wafer image is less sensitive to dose and focus conditions during the exposure. With the increased compute power of latest High-Performance-Clusters (HPC) and the availability of Multi-Beam-Mask-Writers (MBMW) those wafer lithography benefits can be realized at technology nodes currently being developed. A very practical challenge for putting masks with curvilinear shapes in production is the availability of reliable Mask- Rule-Checks (MRC). The OPC engine not only needs to generate shapes which are manufacturable, the mask shop also needs a method of verifying that incoming mask data is manufacturable. For curvilinear mask shapes this is more challenging than for rectangular mask shapes, since simple width and space checks as used for rectangular masks are not sufficient anymore. In this paper, a comprehensive set of MRC limits is being discussed and the effectiveness of an MRC engine operating on curvilinear input data is demonstrated. Rules used here include minimum width of exposed features, minimum space between exposed features, minimum curvature of convex and concave shapes, as well as minimum area of exposed features.

In this paper we present a powerful virtual metrology system to aid in-fab product lot level dispositioning and yield learning. CD and overlay measurement data of different layers are modeled across the wafers and mapped to dense dose, focus, and overlay grids. These are input processing conditions for design-specific computational lithography to predict on full-wafer, full-chip inter-layer overlap area and critical edge-to-edge distances, which are thereafter used to predict electrical failure. The system is composed of an off-line inter-layer hotspot database and an on-line real time dispositioning module. It supports complex multi-patterning stacks with or without self-aligned processes. Example runs have been conducted for 14 nm node metal and via layers, using both FEM-like and typical nominal production wafer data, and the results are as expected from lithographical point of view. Comparing with traditional wafer dispositioning based on static overlay spec and CD spec, our system outputs wafer map stacked with failed dies locations, worst case hotspots contours, root cause analysis, list of worst hotspots and worst dies for inspection, and help litho engineer make an educated decision on wafer dispositioning. This will help fab optimize CD – Overlay process window, improve yield ramp, reduce wafer rework rate, and hence reduce cost, and shorten turn-around-time. The system’s computation is fast and inline real time wafer dispositioning aided by computational lithography is made possible by the system.

It has long been observed that certain pattern-failure phenomena manifest in an apparent random manner on wafer. Thus for a design pattern featuring multiple identical repeats in identical surrounding environments, some locations will at certain processing conditions result in failure, whereas identical patterns in direct proximity might not exhibit failure. Two examples of such are sub-resolution assist features (SRAF) printing and aspect-ratio dependent pattern collapse. SRAFs are of course designed to not print on the wafer, but it is observed that when SRAFs of a certain size or proximity to the main feature, at a specific dose and focus condition, are first observed to print on wafer, they do so in a random manner. The clearest demonstration of this is for a simple grating pattern with long running simple 1D lines interspersed with uniformly sized SRAF on the mask. Depending upon the resist system polarity, it is common to see splotches of partially printed SRAF dimples in the photoresist, or residual scum of photoresist appearing randomly along the length of the SRAM location. This behavior can be ascribed to the cumulative stochastic effects of exposure, PEB, and develop. A more complex phenomenon is pattern-collapse, which has been thoroughly researched and shown to be related to non-uniform capillary forces acting upon the newly developed photoresist pattern as well as the profile and bottom CD of those patterns. The result can again be an apparent randomness to the toppling of patterns which are nominally identical, especially when layout and process conditions are right at the onset of failure observation. Early experimental work in characterizing these two phenomena were often based on simple SEM image analysis, and demonstrated perhaps parts per thousand sensitivity. More sophisticated optical imaging techniques such as E-beam inspection can achieve perhaps parts per million sensitivity. With the advent of EUV lithography, there has been increased attention on stochastic effects, owing to the relatively few number of photons involved in the exposure of a single pattern. The result has been improved experimental methodologies for characterizing stochastic phenomena such as micropinching or micro-bridging, as well as improved simulation of these random behaviors. For 7 nm and below, the required sensitivity to protect yield is less than parts per billion. In this work, we report on the use of stochastic models to quantify the prediction of SRAF printing and pattern-collapse through the process window. Simple grating patterns with variable sized single SRAFs are used for characterization of the failure rate expressed in terms of percent of total SRAF mask layout area in the design block. For pattern collapse simulation, an array of photoresist posts are utilized, and as a proxy for pattern collapse, we use bottom CD area calculated from the randomized simulated contour. We use a range of different stochastic models to represent variable degrees of stochastic contribution and show the impact on main feature line edge roughness (LER) as well as pattern failure. Examples are shown for both EUV and 193i cases, and it is highlighted that stochastic failure is not relegated solely to EUV.

Critical edge placement margins continue to shrink in advanced designs, Over the years, various methods have been used to quantify the lithographic “process window”, often in terms of allowable CD variation. Ultimately however, what is of most interest is the margin for chip failure, either due to hard pinching, bridging, or pattern collapse of a single layer, or interlayer critical edge placement errors. The latter could include insufficient overlap between layers such as metal and via, or unwanted bridging of patterns between layers. We present here a framework for estimating the failure rate for any individual feature given an assumed manufacturing distribution of primary patterning variables such as dose, focus, mask dimension, and perhaps overlay. If the failure rate for all features within the die is known, then by extension the failure rate for the entire die can be known. Since estimating the process window exhaustively for all in-die locations is not possible, we first identify process window limiting features, then utilize this knowledge to estimate overall die failure rates. This method can account for both systematic failure of an individual feature instance as well as stochastic failure for repeating patterns.

Finding the true on-product hot spots (patterning defects) by High Volume Manufacturing (HVM) inspection tools is increasingly challenging as the process window margin shrinks. It is a common practice nowadays to use Optical Rule Check (ORC) results by computation lithography to provide “care areas” to increase the signal to noise level of the inspection tool, thus improving the detection accuracy. The care area defined by the traditional method of contour-based process window checks may not be good enough. There are cases where real yield killers were not caught by contour-based checks, resulting in missing errors during wafer inspection as well. In this paper, we expand the traditional process window checks to a broader lithographic spectrum. The method allows us to utilize additional limiters such as max intensity, contrast, and NILS checks in combination with normal CD-based checks such as bridge, pinch, or process window bands to achieve higher accuracy in failure locations. This compound check will be trained using existing on product failure data obtained from low and high resolution wafer inspection as well as eTest and yield data. The combination of contour and intensity-based checks is demonstrated to be more effective in capturing the wafer hot spots for new products. The various usage models of such enhanced ORC will also be discussed.

In previous work, we have described how EUV scanner aberrations can be adequately simulated and corrected in OPC across the slit to deliver excellent edge placement control. The problem is that the level of aberration variability from tool to tool is currently quite significant and leads to uncorrectable edge placement errors if OPC is done using one tool while exposure happens on a different tool. In this study, we examine the impact of such edge placement errors for single patterning EUV exposure of metal and via layers with variable aberrations in projection lens systems. Two-layer combined CD and overlay edge placement hotspots can be compounded by aberrations which impact CDs and image shifts, and do so differently depending upon design pattern and pupil fill. Aberration values from current 3300 / 3350 EUV scanners are used and compared to hypothetical ideal tool with no aberrations and demonstrate very significant uncorrectable edge placement errors with current aberrations levels. The net result is a significant reduction in the metal-via combined CD-overlay process window.

Edge placement error (EPE) was a term initially introduced to describe the difference between predicted pattern contour edge and the design target. Strictly speaking this quantity is not directly measurable in the fab, and furthermore it is not ultimately the most important metric for chip yield. What is of vital importance is the relative EPE (rEPE) between different design layers, and in the era of multi-patterning, the different constituent mask sublayers for a single design layer. There has always been a strong emphasis on measurement and control of misalignment between design layers, and the progress in this realm has been remarkable, spurned in part at least by the proliferation of multi-patterning which reduces the available overlay budget by introducing a coupling of alignment and CD errors for the target layer. In-line CD and overlay metrology specifications are typically established by starting with design rules and making certain assumptions about error distributions which might be encountered in manufacturing. Lot disposition criteria in photo metrology (rework or pass to etch) are set assuming worst case assumptions for CD and overlay respectively. For example poly to active overlay specs start with poly endcap design rules and make assumptions about active and poly lot average and across lot CDs, and incorporate general knowledge about poly line end rounding to ensure that leakage current is maintained within specification. This worst case guard banding does not consider specific chip designs, however and as we have previously shown full-chip simulation can elucidate the most critical "hot spots" for interlayer process variability comprehending the two-layer CD and misalignment process window. It was shown that there can be differences in X versus Y misalignment process windows as well as positive versus negative directional misalignment process windows and that such design specific information might be leveraged for manufacturing disposition and control schemes. This paper will further investigate examples of via-metal model-based analysis of CD and overlay errors. We will investigate both single patterning and double patterning. For single patterning, we show the advantage of contour to contour simulation over contour to target simulation, and how the addition of aberrations in the optical models can provide a more realistic PW window for edge placement errors. For double patterning, the interaction of 4 layer CD and misalignment errors is very complex, but we illustrate that not only can full-chip verification identify potential rEPE hotspots, the OPC engine can act to mitigate such hotspots and enlarge the overall combined CD-overlay rEPE process window.

In-line CD and overlay metrology specifications are typically established by starting with design rules and making certain assumptions about error distributions which might be encountered in manufacturing. Lot disposition criteria in photo metrology (rework or pass to etch) are set assuming worst case assumptions for CD and overlay respectively. For example poly to active overlay specs start with poly endcap design rules and make assumptions about active and poly lot average and across lot CDs, and incorporate general knowledge about poly line end rounding to ensure that leakage current is maintained within specification. There is an opportunity to go beyond generalized guard band design rules to full-chip, design-specific, model-based exploration of worst case layout locations. Such an approach can leverage not only the above mentioned coupling of CD and overlay errors, but can interrogate all layout configurations for both layers to help determine lot-specific, design-specific CD and overlay dispositioning criteria for the fab. Such an approach can elucidate whether for a specific design layout there exist asymmetries in the response to misalignment which might be exploited in manufacturing. This paper will investigate an example of two-layer model-based analysis of CD and overlay errors. It is shown, somewhat non-intuitively, that there can be small preferred misalignment asymmetries which should be respected to protect yield. We will show this relationship for via-metal overlap. We additionally present a new method of displaying edge placement process window variability, akin to traditional CD process window analysis.

As EUV Lithography is not ready yet for sub-20nm node manufacturing, ArF immersion lithography must extend its capability. Among various double patterning techniques already explored, Litho-Etch-Litho-Etch (LELE) is one of the main streams considered today to continue scaling at 20nm and below. Our paper presents an application of a new OPC algorithm designed to ensure a successful double patterning process at 20nm node. A novel OPC technique was applied to 20nm contact and M1 layers. It is intended for both double and multi-patterning lithography technologies providing model based capability for concurrent correction of the split layouts ensuring a robust stitching overlap of the cut features and preventing inter-mask bridging. We have also developed an OPC verification methodology for DP failures due to dose, focus, mask and overlay errors. One of the most critical challenges of DP technology is: ensuring sufficient stitching of the cut design shapes and preventing a risk of inter-mask shape bridging. This problem is rapidly exacerbated by the overlay error. It is demonstrated that the new OPC algorithm results in enhanced stitching overlap and a good space control between inter-mask shapes, thus, minimizing DP process implications on circuit reliability.

Model-based Optical Proximity Correction (OPC) usually takes into consideration optical and resist process proximity effects. However, the etch bias proximity effect usually can not be completely eliminated by etch process optimization only and needs to be compensated for in OPC flow for several critical layers. Since the understanding of the etch process effect is getting better and accurate etch bias modeling is available now, lithographers start to migrate from rule-based correction to model-based correction. Conventionally when etch bias is considered in model-based correction, optical/resist/etch effect is corrected in one step by using the input layout as the final etch target. In this paper, we proposed a new flow in which etch and optical/resist process effect are separated in both model calibration and layout correction. This double separation allows easier control over etch and resist target, resulting in drastic reduction of OPC runtime. In addition it enables post-OPC verification at both resist and etch level. Advantages of the new integrated model-based retarget/OPC flow in RET implementation are also discussed.

Sub-resolution assist features (SRAFs) or scatter bars (SBs) have steadily proliferated through IC manufacturer data preparation flows as k1 is pushed lower with each technology node. The use of this technology is quite common for gate layer at 130 nm and below, with increasingly complex geometric rules being utilized to govern the placement of SBs in proximity to target layer features. Recently, model based approaches for placement of SBs has arisen. In this work, the variety of rule-based and model-based SB options are explored for the gate layer by using new characterization and optimization functions available in the latest generation of correction and OPC verification tools. These include the ability to quantify across chip CD control with statistics on a per gate basis. The analysis includes the effects of defocus, exposure, and misalignment, and it is shown that significant improvements to CD control through the full manufacturing variability window can be realized.

In our continued pursuit to keep up with Moor's Law we are encountering lower and lower k1 factors resulting in increased sensitivity to lithography / OPC un-friendly designs, mask rule constraints and OPC setup file errors such as bad fragmentation, sub-optimal site placement, and poor convergence during the OPC application process. While the process has become evermore sensitive and more vulnerable to yield loss, the incurred costs associated with such losses is continuing to increase in the form of higher reticle costs, longer cycle times for learning, increased costs associated with the lithography tools, and most importantly lost revenue due to bringing a product to market late. This has resulted in an increased need for virtual manufacturing tools that are capable of accurately simulating the lithography process and detecting failures and weak points in the layout so they can be resolved before committing a layout to silicon and / or identified for inline monitoring during the wafer manufacturing process. This paper will attempt to outline a verification flow that is employed in a high volume manufacturing environment to identify, prevent, monitor and resolve critical lithography failures and yield inhibitors thereby minimizing how much we succumb to the aforementioned semiconductor manufacturing vulnerabilities.

Inverse microlithography solves problem of finding the best mask to print target layout. We present theoretical analysis of objective functions and algorithms that are used for inversion. We analyze complexity, speed and limitations of the inverse algorithms.

Besides models describing the exposure tool optical system, lumped parameter resist models are the other important model used during OPC. This combination is able to deliver the speed and accuracy required during OPC. Lumped parameter resist models are created by fitting a polynomial to empirical data. The parameters of this polynomial are usually image parameters (maximum and minimum intensity, slope, curvature) taken from the optical simulation for each measured structure. During calibration of such models, it is very important to pay attention to the parameter space covered by the calibration pattern used. We analyze parameter space coverage for standard calibration patterns, real layout situation post OPC correction as well as pre OPC correction. Taking this one step further, the influence of parameter space coverage during model calibration on OPC convergence is also studied.

SMIC is a pure-play IC foundry, as foundry culture Turn-Around Time is the most important thing FABs concern about. And aggressive tape out schedule required significant reduction of GDS to mask flow run time. So the objective of this work is to evaluate an OPC methodology and integrated mask data preparation flow on runtime performance via so-called 1-IO-tape-out platform. By the way, to achieve fully automated OPC/MDP flow for production. To evaluate, we choose BEOL layers since they were the ones hit most by runtime performance -- not like FEOL, for example, Poly to CT layers there're still some non-critical layers in the between, OPC mask makings & wafer schedules are not so tight. BEOL, like M2, V2,then M3 V3 and so on, critical layer OPC mask comes one by one continuously. Hence, that's why we pick BEOL layers. And the integrated flow we evaluated included 4 layers of metal with MB-OPC and 6 layers of Via with R-B OPC. Our definition of success to this work is to improve runtime performance at least of larger than 2x. At meantime, of course, we can not sacrifice the model accuracy, so maintaining equal or better model accuracy and OPC/mask-data output quality is also a must. For MDP, we also test the advantage of OASIS and compared with GDS format.

Using a commercialized product Calibre OPC platform, optical and process models were built that accurately predict wafer-level phenomena for a sub-90nm poly process. The model fidelity relative to nominal wafer data demonstrates excellent result, with EPE errors in the range of ±2nm for pitch features and ±7 for line-end features. Furthermore, these models accurately predict defocus and off-dose wafer data. Overlaying SEM images with model-predicted print images for critical structures shows that the models are stable and accurate, even in areas especially prone to pinching or bridging. In addition, process window ORC is shown to identify potential failure points within some representative designs, allowing the mask preparation shop to easily identify these areas within the fractured data. And finally, the data and images of mask hotspots will be shown and compared down to wafer level.

Use of simulation-based printing verification prior to mask tapeout has become standard practice for mask layers printed with low-k1 lithography processes. At 90nm and above, this methodology has proven beneficial and sufficient for guaranteeing a usable mask. However, it is anticipated that at 65nm and below, a simulation at a single point within the process window may fail to capture all important marginal areas of a mask prior to tapeout. Modern lithography simulation tools are proven capable of accurately predicting printing behavior through process window. Unfortunately, due to long run times, use of such tools is restricted to small simulation areas. Recent developments in vectorial thin-film OPC models have enabled full process window prediction on large product die. Although such models are extremely fast compared to conventional lithography simulation tools, the prospect of simulating a full chip at multiple dose and focus points is quite daunting. In an effort to reduce the expected longer run times when simulating full chips at multiple focus and dose conditions, we have developed two flows which reduce the total run time enormously. These so-called pre-targeting flows are explained, and the limitations and future prospects of the flows are described.