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International Technology Roadmap for Semiconductors (ITRS) is referred to as one of the most successful roadmapping attempts in high-tech industries. ITRS constantly gave orientation to industries (device/equipment/materials), academia, and governments for continuing miniaturization. The 2000s, the period of utmost attention to ITRS, is also the period of gradual “breakdown” of Dennard's Scaling Law which stipulates the “technological merits” attained by miniaturization of Si-CMOS semiconductors: 1) shrink in chip size; 2) lowered power consumption, and 3) boosted computation speed, simultaneously. The author discusses that ITRS of 2000s had worked for “recovering” the “breakdown” of the Law and that it is attributed to the highly structured nature of Si-CMOS semiconductor technologies in a frame of “(manufacturing) process–device structure–function.” Then, he evaluates the validity of the hypothesis by analyzing wide range of technologies newly introduced in 2000s, namely 1) variety of supplementary methods for “prolonging” the life of Argon Fluoride Laser lithography; 2) high-k dielectric membranes and metal gate for reducing gate-leak current; and 3) low-k dielectric membranes and strained-silicon transistors to boost computation speed. Thus, the author concludes that 1) ITRS at least functioned to let the consensus (among early adopters) be “established” in wide range of research community; 2) under the “gradual breakdown” of Dennard's Scaling Law in 2000s, ITRS worked to keep the Si-CMOS semiconductor's “killing-three-birds-with-one-stone” nature; and 3) the success of ITRS in 2000s is attributed to the structural frame of Si-CMOS semiconductor technologies characterized as “fixed-in-total and disruptive-in-parts.” [ABSTRACT FROM AUTHOR]

Integration of silicon-complementary metal oxide-semiconductor (Si-CMOS) and III-V compound semiconductors (with device structures of either InGaAs HEMT, AlGaInP LED, GaN HEMT, or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN HEMT or LED on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.