43 results on '"Singanamalla, R."'
Search Results
2. Performance enhancement of Poly-Si/TiN/SiON based pMOSFETs by addition of an aluminum oxide (AlO) capping layer
3. Effect of degas before metal gate deposition on the threshold voltage
4. Growth of epitaxial CoSi2 from Cobalt Carbonyl on Si(100) Substrate
5. Gate electrode effects on low-frequency (1/ f) noise in p-MOSFETs with high-κ dielectrics
6. Single-Wafer Wet Chemical Oxide Formation for Pre-ALD High-k Deposition on 300 mm Wafer
7. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
8. Multi-VT engineering in highly scaled CMOS bulk and FinFET devices through Ion Implantation into the metal gate stack featuring a 1.0nm EOT high-K oxide
9. A VFB tunable Single Metal Single Dielectric approach using As I/I into TiN/HfO2 for 32nm node and beyond
10. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
11. N-type VT tuning by Te ion implantation in moly-based metal gates with high-k dielectric for fully depleted devices
12. Effective Work-Function Modulation by Aluminum-Ion Implantation for Metal-Gate Technology $(\hbox{Poly-Si/TiN/SiO}_{2})$
13. Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal
14. Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $\hbox{Dy}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics
15. Treshold voltage modulation in FinFET devices through Arsenic Ion Implantation into TiN/HfSiON gate stack
16. Demonstration of Metal-Gated Low $V_{t}$ n-MOSFETs Using a Poly-$\hbox{Si/TaN/Dy}_{2}\hbox{O}_{3}/\hbox{SiON}$Gate Stack With a Scaled EOT Value
17. A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM
18. Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases
19. Nitrogen Profile and Dielectric Cap Layer (Al2O3, Dy2O3, La2O3) Engineering on Hf-Silicate
20. Electrical Properties of nMOSFETs Using the NiSi:Yb FUSI Electrode
21. Tuning PMOS Mo(O,N) metal gates to NMOS by addition of DyO capping layer
22. Metal Inserted Poly-Si (MIPS) and FUSI dual metal (TaN and NiSi) CMOS integration
23. The Impact of Ultra Thin ALD TiN Metal Gate on Low Frequency Noise of CMOS Transistors
24. Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack
25. Low VT Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET Devices
26. Advanced Ni-based Fully SIlicidation (FUSI) technology for sub-45nm CMOS devices
27. Gate electrode effects on low-frequency (1/f) noise in p-MOSFETs with high-κ dielectrics
28. On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks
29. Demonstration of a New Approach Towards 0.25V Low-Vt CMOS Using Ni-Based FUSI
30. Growth of epitaxial CoSi2 from Cobalt Carbonyl on Si(100) Substrate
31. Demonstration of phase-controlled Ni-FUSI CMOSFETs employing SiON dielectrics capped with sub-monolayer ALD HfSiON for low power applications.
32. Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON.
33. Growth of epitaxial CoSi2 from Cobalt Carbonyl on Si(100) Substrate.
34. Achieving LOW-VT Ni-FUSI CMOS by Ultra-Thin Dy2O3 Capping of Hafnium Silicate Dielectrics.
35. Effective Work-Function Modulation by Aluminum-Ion Implantation for Metal-Gate Technology (Poly-Si/TiN/SiO2).
36. Demonstration of Metal-Gated Low Vt n-MOSFETs Using a Poly-Si/TaN/Dy2O3/SiON Gate Stack With a Scaled EOT Value.
37. On the Impact of TiN Film Thickness Variations on the Effective Work Function of Poly-Si/TiN/SiO2 and Poly-Si/TiN/HfSiON Gate Stacks.
38. Tall triple-gate devices with TiN/HfO/sub 2/ gate stack
39. Multi-VT engineering in highly scaled CMOS bulk and FinFET devices through Ion Implantation into the metal gate stack featuring a 1.0nm EOT high-K oxide.
40. Demonstration of a New Approach Towards 0.25V Low-Vt CMOS Using Ni-Based FUSI.
41. Tall triple-gate devices with TiN/HfO2 gate stack.
42. Gate-dielectric interface effects on low-frequency (1/f) noise in p-MOSFETs with high-K dielectrics.
43. Achieving low-V T Ni-FUSI CMOS via lanthanide incorporation in the gate stack
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.