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A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. We then performed 400 virtual experiments comprising seven sources of process variation. Using this virtual fabrication technique, we were able to identify a minimum gate-to-source/drain spacer thickness for a high-temperature post-EPI rapid thermal anneal (RTA) anneal process that avoided device subthreshold slope penalties. The model allowed us to determine the optimal Si recess depth target and process window prior to source/drain epitaxy. We obtained these results by reviewing device performance as a function of statistical process sensitivity and highlighting key process parameters requiring variation control. These experiments would have been impractical to perform in an actual fab, due to the time, cost, and equipment requirements of running 400 fab-based process variation experiments for each process parameter. This methodology can be used to avoid wafer-based testing during early technology development.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

We evaluate the reliability of barrierless Mo metallization on various dielectrics that are used in both BEOL and MOL integration schemes. In particular, we assess the risk of metal drift-induced failure in SiO 2 , LK3.0, SiCO and Si 3 N 4 films by performing TDDB measurements on MIM planar capacitors. We show that Mo does not drift in SiO 2 , LK3.0, and SiCO. Despite a thoroughly failure analysis no definitive conclusion could be reached for the Si 3 N 4 films.

In this study, we explored the key properties and functionalities of plasma enhanced atomic layer deposition (PEALD) SiNx films, synthesized using different deposition temperatures (500–550 °C) and plasma conditions (lower and higher), both on 300 mm blanket Si and on several integrated 3D topology substrates, at the thicknesses relevant for diverse nanoscale applications. Our study shows that with an increase of temperature (500–550 °C), a small reduction in HF wet etch rate (1.1–0.69 nm/min), and H content (9.6% vs 7.4%) was observed. When using higher plasmas, significant improvements in blanket properties were observed. The films were denser (2.95 g/cm3), exhibited lower H content (2.4%), showed better etch rates (0.39 and 0.44 nm/s for HF and CF4 based), and SiNx grew without any nucleation delay on alternative Si1−xGex channel surfaces. The vertical and lateral conformality was found to be similar and appears not to be impacted with the plasma conditions. Extensive steam oxidation barrier studies performed at the sidewalls of different aspect ratio lines showed the PEALD SiNx liner scaling potentiality down to 1 nm when deposited using higher plasma. In addition, the outer gate and inner spacer properties were found to be superior (with lower loses) for higher plasma films when subjected to several dry etch, strips, and H3PO4 chemistries. The outstanding conformality (90%–95% on aspect ratios ≤10:1) combined with excellent high end material properties in the ultrathin regimes (1–10 nm) corroborate the virtue of PEALD SiNx toward integration in scaled down and advanced nanoelectronics device manufacturing.

This paper reports BPR/Via-to-BPR (VBPR) module development at 24nm fin pitch (FP) / 42nm contacted gate pitch (CPP), and W and Ru-BPR and Ru- Contact-to-Active (M0A)/VBPR resistance (R) & electromigration (EM). BPR dielectric barrier, BPR plug barrier, and fin reveal are optimized to enable BPR scaling. A self-aligned VBPR etch is also demonstrated by Q-ALE process. Ru-BPR meets BPR line R target target 1100 h at 5 MA/cm2 at 330 °C.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

Top tier devices in a 3D sequential integration are optimized using a low temperature process flow $( . Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar $\mathrm{I}_{\mathrm{on}}-\mathrm{I}_{\mathrm{off}}$ device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion.

We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.

An inverter is a basic electronic device used repeatedly in larger circuitry. The performance and overall power handling depend on the design of the $\pmb{N}$ and PMOS transistors and on the circuit itself. In our study, we model a representative 24 nm fin pitch and 42 nm gate pitch inverter using Coventor SEMulator3D® Virtual Platform. We have investigated an initially deposited spacer thickness process window of 3 nm to 10 nm and a gate width variation from 14 nm to 18 nm. DC performance calculated using drift diffusion, was optimized for junction anneal time, considering a figure of merit using $\pmb{I}_{on}$ & DIBL for both NMOS & PMOS. AC performance was evaluated with an Elmore delay model, using the drift diffusion-based DC data combined with RC netlist data. Circuit speed gain is obtained with gate length scaling down to 14 nm, but lack of junction abruptness limits the benefit of deposited spacer scaling below 7 nm.

Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaining low off-state leakage [1]. Besides, horizontally oriented nanowires are an evolutionary extension of FinFETs, as opposed to vertical nanowires which require more disruptive technology and design changes [2]. Finally, stacking of nanowires is relevant for enhancing the drive current per footprint. Based on these considerations, GAA transistors made of vertically stacked horizontal nanowires have been included in the ITRS roadmap to reduce the contacted gate pitch, which is a key figure of merit for CMOS device density, to below ~40 nm in 2019-2021 [3]. In the context of the industrial relevance described above, we present the fabrication of Si GAA devices on bulk Si substrates. Multiple processing aspects that are relevant for bulk CMOS technology definition are addressed, including stacking of 8-nm-diameter Si wires at 45-nm lateral pitch and 20-nm vertical pitch [4], and nanowire-compatible replacement metal gate processing in combination with threshold voltage tuning by dual work function metal integration [5]. Temperature restrictions for the formation of shallow trench isolation, and the interaction between N- and P-type junction formation on one hand and nanowire release processes on the other hand are discussed as well. [1] K. J. Kuhn, IEEE Trans. Electron Devices, vol. 59 (7), p.1813, (2012). [2] L. Liebmann et al., VLSI Tech. Dig., p.112 (2016). [3] The International Roadmap for Semiconductors (ITRS) 2.0, http://www.itrs2.net/ (2015). [4] H. Mertens et al., VLSI Tech. Dig., p.158 (2016). [5] H. Mertens et al., IEDM Tech. Dig., p.524 (2016). Figure 1

We demonstrate multiple ways to reduce the D IT of Si-cap-free low-Ge-content (25-30%) SiGe gate stack. The D IT is reduced by i) Ge oxide scavenging via Ge condensation or by the work function metal (WFM), ii) nitridation of gate dielectrics and iii) optimized high-pressure anneal (HPA). A moderate nitridation of the interface layer (IL) is beneficial in EOT and D IT reduction, while nitridation of the HfO 2 dramatically reduces D IT by negating an ALD TiN-induced D IT increase. The optimized gate stack is evaluated in 8-nm-wide strained Si 0 7 Ge 0 3 pFinFETs integrated on 300 mm Si wafers, for which a 35% improvement in high-field mobility is demonstrated as compared to Si pFinFET counterparts.

This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(\text{L}_{\text{G}}\sim 25\text{nm})$ compared to our previous work. Excellent electrostatic control is maintained down to $\text{L}_{\text{G}}=25$ nm by using extension-less scheme, while the performance is kept by appropriate spacer scaling and implementation of highly B-doped Ge or GeSn as source/drain (S/D) material.

3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSi x ) and achieve ultralow contact resistivity ( $\rho _{c}$ ) of (1.3 – 1.5) $\times 10^{-9} ~\Omega \cdot \text {cm}^{2}$ on Si:P. This PCAI + TiSi x technique utilizes light amorphization (low-energy implantation), thin Ti and TiSi x film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSi x -induced $\rho _{c}$ reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced $\rho _{c}$ variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low $\rho _{c}$ is strongly correlated with the formation of interfacial TiSi x crystallites between amorphous TiSi alloy and Si.

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1- $\mu \text{m}$ and 70-nm gate lengths. Hole mobility at 1- $\mu \text{m}$ gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.

This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height ( $q\varphi _{b})$ MIS contact: Ti/TiO2/n-Si. By incorporating different levels of donor concentration in n-Si, we perform a systematic Ti/TiO2/n-Si thermal stability study under different electron conduction mechanisms. We find that both $q\varphi _{b}$ and contact resistivity ( $\rho _{c})$ of the Ti/TiO2/n-Si MIS contacts vary dramatically after mere 300 °C–500 °C 1-min rapid thermal treatments. The variations in $q\varphi _{b}$ and $\rho _{c}$ are related to the thermally driven TiO2 decomposition. This thermal stability study of Ti/TiO2/n-Si reveals a general concern for the MIS contact application: since the MIS contacts on n-type semiconductor generally utilize a reactive low-work function metal and an ultrathin insulator, it is difficult to maintain their interface quality considering the thermal budget in standard manufacturing of integrated circuits. Possible solutions to this MIS thermal stability issue are discussed.

In 5 nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24 nm. Fin depopulation is mandatory to enable the area scaling, but it becomes challenging at small pitches. In the first part, each process flow is simulated in order to obtain a 3D model of a FinFET SRAM device. Layout dependent effects on silicon and process non-idealities are characterized in a second part and used to calibrate the 3D model. In the third part, a process sensitivity analysis is conducted to compare the impact of overlay and CD variations on various options.

3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(\mathrm{T}\leq 525^{\circ}\mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature.

The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework. Through a double level access it offers a structural scaling of both standard cells (SDC) and SRAM by 50%. The proposed process flow requires accurate control of the elevation dimension for manufacturability. Based on TCAD analysis, the CFET can eventually outperform the finFET device and meet the N3 targets in power and performance. To achieve that, the dominating parasitic resistance of the deep vias needs to be reduced by the introduction of advanced MOL contacts featuring thin barriers.

In this work, we propose replacement metal contact (RMC) flow by using sacrificial ILD0 that is suitable for wrap around contact (WAC). RMC minimize erosion of gate plug, spacer and S/D area at scaled contact formation. The concept of the flow has been demonstrated in short loop flow with ~50% contact resistance improvement for both NMOS, Si:P and PMOS, SiGe:B.

We look at several scaling boosters necessary to accomplish CMOS area scaling towards the 2nm node. We consider aspects of standard cell area scaling, transistor architecture, SRAM, and BEOL. We also demonstrate integrated flows and hardware feasibility for such scaling boosters.

We report on CMOS-integrated vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs with in-situ doped source-drain stressors and dual work function metal gates. We demonstrate that oxidation-induced SiGe/Si fin deformation by STI densification is effectively suppressed by a SiN liner. This SiN fin protection improves the controllability of nanowire formation. In addition, highly-selective Si nano-wire release and inner spacer cavity formation without Si re-flow are demonstrated. Finally, for the first time we report functional ring oscillators based on stacked Si NW-FETs.

We report on Atomic Layer Deposition Titanium (ALD Ti) for FinFET source/drain contact applications. On planar test structures, we accurately benchmark contact resistivity (ρc) of ALD Ti, ∼1.4×10–9 Ω·cm2 on Si:P and ∼2.0×10–9 Ω·cm2 on SiGe:B, among to lowest reported values in literature. Ultralow ρc is resulting from enhanced Ti/Si(Ge) reactivity originating in the ALD process. We also demonstrate capability of this process to significantly lower Rc on FinFETs by allowing a lateral contact into the S/D area effectively maximizing the contacting area.

Different metallization options that allow filling 30nm 1/2pitch interconnect trenches have been explored and their full reliability performance has been benchmarked to conventional PVD TaNTa/PVD Cu seed based metallizations. CVD Co as seed enhancement layer shows no deterioration in barrier performance and improved electromigration performance, but the activation energy for electromigration was 0.68+/-0.20eV, which is at the lower end of the expected value of 0.85-0.95eV for this parameter. When integrating our trenches in a k=3.2 non-porous SiCOH low-k material, PVD RuTa barriers with 90%Ru and 10%Ta show degraded barrier performance and significant lowering of activation energy for electromigration (0.59+/-0.05eV) while when using SiO"2 as intermetal dielectric, no significant reliability deterioration is observed. Finally, it is shown that, using an optimized PVD Cu seed, standard PVD TaNTa-barriers give excellent barrier performance and that typical electromigration lifetime specs can be met with this metallization scheme down to 30nm 1/2pitch.

We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.

For the first time, we have established a replacement metal gate complementary metal-oxide-semiconductor process flow for the high temperature ion implantation of bulk Si fin field-effect-transistors on a 45-nm fin pitch design rule, using high temperature spin-on-carbon hard mask and a dedicated patterning process. In this paper, the advantages of high temperature ion implantation and a detailed process flow of the dedicated patterning are explained. Electrical characteristics of metal-oxide-semiconductor field-effect-transistors and ring oscillators are evaluated.

This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs/n-Si, and n-InAs/n-Ge; and that 2) a TiSi x /12nm Si:P/n-Ge contact with favorable band alignment between Si:P/n-Ge approaches low effective contact resistivity of 1.4×10−8 Ω cm2, close to a record-low value for n-Ge contacts.

We demonstrate the effectiveness and limitations of critical performance elements in silicon channel bulk finFET CMOS devices featuring embedded Source/Drain (e_SD) dual epi. Further scaling of the fin width below 10nm is shown to impact both the access resistance and S/D overlap capacitances while the mobility behavior for both nMOS and pMOS devices further degrades. Epitaxial S/D regrowth options are optimized to demonstrate ring-oscillator functionality for fin width down to ∼4nm.

Following the previous study on Si:P [1], we also achieve ultralow contact resistivities (ρ c ) of ∼2×10−9 Ω·cm2 on Si 0.3 Ge 0.7 :B using the same Ti based pre-contact amorphization (PCAI) plus post-metal anneal (PMA) technique. Similar as on Si:P, low-energy PCAI provides the lowest ρ c on SiGe:B. By increasing the B concentration, the PMA temperature required on SiGe:B also matches with that on Si:P. A simple Ti based CMOS contact flow is thus proposed. Several B doping and activation methods on SiGe:B are also compared in this work.

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for L G = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

Contact resistance at the transistor source/drain becomes a bottleneck for modern Si CMOS technology. To seek for contact solutions, this paper compares metal-insulator-semiconductor (MIS) contacts and metal-semiconductor (MS) direct contacts in terms of contact resistivity and CMOS compatibility. On p-type substrates, due to the favorable surface Fermi level pinning, MS contact has absolute advantage over MIS. On n-type substrates, on the one hand, we find MIS contacts have relatively high contact resistivity despite the low Schottky barrier height; the low thermal stability of MIS is also worrying. On the other hand, with MS contacts, we use a pre-amorphization based Ti silicidation technique and achieve contact resistivity of 1.5×10−9 Ω·cm2. Therefore, for both NMOS and PMOS, we confirm that MS contacts are still the prevailing contact scheme. Advanced MS interface engineering is able to help reach the target contact resistivity required by advanced CMOS technology.

This paper introduces the investigations on ultralow metal/semiconductor contact resistivity (ρc). First, we build a multiring circular transmission line model (MR-CTLM), a novel ρc test structure with simple process and high accuracy for rigorous ρc study. Based on that, we explore process options to achieve ultralow ρc on n-Si. We obtain high carrier concentration of ∼9e20 cm−3 by in situ P doped Si:P epitaxy followed by ms laser annealing. Besides, we use a pre-contact amorphization plus Ti silicidation technique to fabricate TiSix/Si:P contacts and achieve ultralow ρc of 1.5e–9 Ohm.cm2. Finally, we discuss sub-1e-9 Ohm.cm2 ρc solutions for future CMOS technology node.

A time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed. The structure, validity, and accuracy of the model are evaluated and discussed. The model is applied to an interconnect scaling scenario that includes conventional patterning and spacer-defined patterning of nanometer-scale Cu wires. LER-aware TDDB lifetime predictions are obtained from the model, and consequent recommendations on how to improve the TDDB lifetime of future interconnects are derived.

The traditional Cu interconnect barrier/seed process consisting of PVD-Ta based barrier/Cu-seed will reach its limit between 20 nm and 30 nm wide trench dimension. To extend Cu interconnect technology further, possible solutions such as PVD-RuTa, PEALD-Ru-based, CVD-Co, PVD/CVD-self-formed-MnSixOy and self-assembled monolayers (SAMs) are studied. It is shown that both PVD-RuTa and CVD-Co possess the so-called seed enhancement capability allowing Cu filling of narrow recesses. However, they exhibit limitations in terms of Cu-diffusion barrier efficiency, electromigration reliability and scalability. Despite, the concept of SAM [NH2-SAM(C3)] as Cu diffusion barrier is demonstrated, it requires maturity and compatibility within the process flow (e.g. adhesion with the Cu overlayer). Finally, it is considered that PEALD-Ru-based alloys and CVD-based MnSixOy films are serious candidates for sub-30 nm wide trench technologies because of their conformal nature and ability to act as an efficient Cu diffusion barrier in the range of 2 nm thickness.

Two types of wet cleaning solutions were screened for post etch residue removal in back end of line applications: aqueous acid chemistries and organic solvents. Their compatibility with plasma damaged low-k materials and their polymer removal efficiency were checked on blanket low-k layers and single damascene layers, respectively. Aqueous acid chemistries under study showed either to be compatible with plasma damaged low k material but had poor polymer removal efficiency, or showed good polymer removal but also removal of the plasma damaged low-k. A correlation between the damaged low-k and the amount of etching additive in aqueous acid chemistry could be established. Initial tests with organic solvents demonstrated that they were compatible with the damage low-k layer. Concerning polymer removal, some partial dissolution of polymers was observed for the first time. Furthermore, the cleaning performance of organic solvents, and hence the electrical performance, can be improved by applying megasonic power during the clean process.

As an alternative to W contacts currently used in MOSFETs for DRAM, Cu contacts using self-aligned Ta-silicide and Ta-based barrier were studied experimentally. The silicidation of PVD Ta layers was studied first on 300mm blanket Si wafers. The developed method was applied to patterned wafers in the contacts, that land on poly gate and active areas of NMOS, with a sequence including the PVD of Ta, a silicidation annealing, a Ta-based Cu diffusion barrier and a Cu seed for plating the Cu plug. X-ray diffraction (XRD), X-ray reflection (XRR) and sheet resistance tests of the blanket wafers show that a Ta layer of about 10nm reacts with Si substrate and forms TaSi"2 at 650^oC in a reducing ambient. Cross-sectional SEM observation reveals that the selected processing flow fills the 90nm contacts. Top-view SEM observation on the samples after 420^oC sintering demonstrates that the Cu diffusion barrier is effective. I"o"n-I"o"f"f curves of the devices show a performance for NMOS comparable to the reference samples which use Ni(Pt)Si and the same barrier and Cu contacts, indicating that the stack of the barrier/TaSi"2/p-type Si has a contact resistance comparable to the barrier/Ni(Pt)Si/p-type Si.

Manufacturable processes to reduce both channel and external resistances (RExt) in CMOS devices are described. Simulations show that RExt will become equivalent to strained Si channel resistance near the 32-nm logic node. Tensile stress in plasma-enhanced chemical-vapor-deposited SiNx liners is increased with UV curing, boosting the NMOS drive current by 20% relative to a neutral reference. W contact-plug resistance (Rc) is reduced by 40% by optimizing preclean, liner/barrier, and nucleation steps. Replacing the fill material with Cu reduces Rc by > 35% as compared to W. The Schottky barrier height of silicide contacts to p-Si is reduced by 0.12 eV with a 10% addition of Pt, resulting in a ~10% increase in the PMOS drive current. By implementing a two-step anneal process (spike + laser), the source/drain-extension resistance can be reduced by 20%.

PVD Ta-based and ALD TaN layers were studied as Cu diffusion barriers on poly-silicon, NiSi and CoSi"2 for Cu contact applications. The effectiveness of nanometer-thick layers, deposited in manufacturing compatible chambers on 200 and 300mm wafers, is evaluated by detection of Cu-silicidation temperature using high temperature in situ XRD. It is found that Si diffuses into the @a-Ta lattice for PVD barriers between 300 and 500^oC, and induces Ta silicidation at 600^oC. The agglomeration of TaSi"2 seems to be responsible for the damage of barrier continuity and cause subsequent Cu-silicidation. The growth of ALD TaN on different surfaces of NiSi was studied by XRF, RBS and XRR. The growth curves show excellent linearity as a function of thickness. TOF-SIMS shows closed layers after 60 ALD cycles. In situ XRD reveals that the failure temperature of 4nm thick ALD layers is higher than 500^oC. It is found that the failure of 3 and 4nm ALD TaN layers in Cu/barrier/NiSi stacks is a diffusion controlled process, with an activation energy Q of ~2.2eV and a pre-exponential factor D"0 of ~3.8x10^-^3cm^2/s.

For the PMD in a next generation memory device, two kinds of newly developed ultra low-k MSQ materials (k 500^oC. The thermal stability of the low-k MSQ is correlated with the amount of Si-X (X=H or CH"3), the ratio of Si-X to Si-O, and the structure of the Si-O bonds. With PE-SiO"2 and PE-SiN capping on HSQ, the k-value of

For every new technology node, the specifications for different processing steps become more stringent. For cleaning, one strives to continuously reduce the loss of substrate and film thickness while maintaining a high cleaning efficiency. Short and well-controlled chemical exposure times are desired and may enable the use of more aggressive chemistries. Reducing delay time between etching and subsequent wet clean, by introducing clustered processing, may allow for more effective residue removal. This paper describes a novel cleaning concept, Confined Chemical CleaningTM, and its application in post contact etch residue removal. The technique combines short and controlled exposure times with clustered processing for residue removal.

We demonstrate a NMOS Si Bulk-FinFET with extension doped by Phosphorus doped Silicate Glass (PSG). Highly doped PSG (6e21 cm−3) was used as a diffusion source. SiO2 cap on PSG decreased sheet resistance (Rs) due to less out diffusion of P. Even when thin SiO2 exists at the interface between Si and PSG, P diffused from PSG into Si. Thanks to the high etch rate of the PSG/SiO2 cap stack after drive-in anneal, the PSG/SiO2 cap was successfully removed by HF with minimum removal of STI and gate hard mask oxide. PSG provides damage free and uniform sidewall doping to fin. On current ION is improved by 20% for LG in the 30–24 nm range, with similar IOFF and better DIBL compared to P ion implanted reference.