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A two-step analog accumulator structure, fit for CMOS time-delay integration image sensor, is proposed to combat the impacts of parasitic phenomenon of the traditional one-step analog accumulator. To implement the two-step accumulation, the exposure signals are divided into groups. The synchronous signals in each group are integrated in step1 integrators, which are designed based on the switched-capacitor amplifier. Then, the integral signals from step1 are integrated in step2 integrators. The temporal undersampling exposure method is adopted in the sensor to reduce the number of integrators. Two versions of a prototype 64-stage two-step accumulator, with and without the decoupling capacitance $C_{d}$ , are designed and fabricated in 0.18- $\mu \text{m}$ one-poly four-metal 1.8 V/3.3 V CMOS technology. With an $8 \times 8$ stepping pattern, the signal-to-noise ratio improvements of the two versions are 17.278 and 17.192 dB at 64 stages, respectively, while the ideal value is 18.062 dB. The experimental results have proved the effectiveness of the two-step structure in combating the parasitic phenomenon and made the analog accumulator with higher stage realizable.

Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect.

A radiation hardened by design (RHBD) latch and its temporally hardened version to tolerate double node upsets are proposed in this paper. C-Elements are used to construct structures for fault correction. The temporally hardened version can further tolerate some single-event transients (SETs) at input port and clock line. Compared with Quintuple Modular Redundancy (QMR), the proposed non-temporally and temporally hardened latches are more area and power efficient with improved propagation delays. Compared with several previously reported temporally hardened latches, the proposed temporally hardened latch may introduce lower performance loss induced as setup time increase. Several multi-node upset tolerant latches are also compared with these two designs in terms of area, power, and delay. A cell level soft error analysis (TFIT) shows that the upset threshold LETs of the proposed latches in 180 nm process are higher than 16 MeV-cm2/mg.

This paper presents an in-pixel dual exposure synthesis technique to extend dynamic range of CMOS image sensors (CISs). The transfer transistor of the 4-T pixel acts as an overflow transistor in this proposed method. The full well capacity of photodiode (PD) can be very well controlled by biasing the transfer gate at different states. The long and short time exposed signals can be both stored in PD by adjusting the transfer gate voltage, and such the wide dynamic range signal can be obtained without extra readout operation. A proto chip with $64 \times 48$ pixel array is fabricated in 0.18- $\mu $ m CIS process. The sensor structure is based on a typical 4-T pixel image sensor with modified transfer gate driver and timing. This structure not only maintains the good features of 4-T pixels, such as good fill factor and low noise, but also achieves a wide dynamic range. The dynamic range of the proto chip is extended from 51.59 to 90.53 dB.

Task mapping strategies on NoC (Network-on-Chip) have a huge impact on the timing performance and power consumption. So does the topology. In this paper, we describe the exploration flow of task mapping algorithms using different NoC mesh shapes. The flow is used to evaluate timing and energy consumption based on a NoC emulation platform. It is open to any task mapping algorithms and to any shapes of NoC mesh. A heterogeneous (PC and FPGA) platform is used to fully perform each step of the flow. The experiments demonstrate that the most appropriate task mapping strategy and the most suitable NoC shape strongly depend on the algorithm used. Depending on the timing latency results obtained and the FPGA resources used, the designer can select the appropriate task mapping strategy on the suitable shape in a short exploration time and with precise timing evaluation.

An analytical model of Modulation Transfer Function (MTF) for Time-Delay-Integration CMOS Image Sensor (TDI-CIS) in the scanning direction is proposed. Impacts of pixel valid sensitive ratio, scanning efficiency, velocity mismatch ratio and TDI stage on MTF are studied based on the analysis of TDI-CMOS temporal oversampling rolling-shutter readout timing principle. By establishing a TDI-CIS imaging-simulation system according to geometric perspective and light transmission relationship from continuous known objects to a discrete image on the pixel plane, simulations of TDI-CIS imaging process under different circumstances are carried out. Then knife-edge method is used to calculate MTF of the TDI image. The simulation results show that MTF is inversely proportional to valid sensitive ratio and scanning efficiency. MTF keeps steady when velocity mismatch ratio is 0, and it decreases with the increase of TDI stage when velocity mismatch ratios are non-zero values. At the same time, the tendency that the MTF decreases with the increase of velocity mismatch ratio is getting more obvious when TDI stage increases. MTF at a specific frequency can even drop to almost 0 when the velocity mismatch ratio increases to 30 % and the number of TDI stages is 16.

A quasi-constant on-time controlled buck front end in combined discontinuous conduction mode and boundary conduction mode is proposed to improve power factor (PF).When instantaneous AC input voltage is lower than the output bus voltage per period, the buck converter turns into buck-boost converter with the addition of a level comparator to compare input voltage and output voltage. The gate drive voltage is provided by an additional oscillator during distortion time to eliminate the cross-over distortion of the input current. This high PF comes from the avoidance of the input current distortion, thereby enabling energy to be delivered constantly. This paper presents a series analysis of controlling techniques and efficiency, PF, and total harmonic distortion. A comparison in terms of efficiency and PF between the proposed converter and a previous work is performed. The specifications of the converter include the following: input AC voltage is from 90V to 264V, output DC voltage is 80V, and output power is 94W.This converter can achieve PF of 98.74% and efficiency of 97.21% in 220V AC input voltage process.

The impacts of parasitic phenomenon on the performance of the analog accumulator in CMOS TDI image sensor are analyzed in this paper, and a modified accumulator with decoupling capacitor Cd to combat the parasitic phenomenon is also proposed. A 128-stage modified accumulator is designed and simulated. A prototype 1024 × 128 CMOS TDI image sensor with the 128-stage modified accumulator is fabricated in 0.18- μm one-poly four-metal 1.8 V/3.3 V CMOS technology. With a line rate of 3875 lines/s, at 128 stages the measured sensitivity and SNR improvement of the fabricated sensor are 617.1 V/lux·s and 16.6 dB respectively. The simulation and experiment results have proved the effectiveness of the decoupling capacitor C d when combating the parasitic phenomenon in the analog accumulator. The proposed modified accumulator is suitable for application in CMOS TDI image sensor with high stages.

This brief presents a 32-stage CMOS time delay integration image sensor with on-chip column parallel analog accumulator. Temporal oversampling technique is applied in the sensor to realize synchronous signal capturing. A column parallel analog accumulator with layout size of 0.09 mm2 is integrated at both sides of pixel array. Through adopting input-offset storing technique, a column fixed pattern noise because of the amplifier's offset variations is reduced by the accumulator. The accumulator also acts as a pixel noise canceller. The fabricated chip in 0.18- μm one-poly four-metal 1.8/3.3-V CMOS technology achieves the maximum line rate of 3875 lines/s. The measured signal-to-noise ratio of the fabricated sensor is improved on average by 11.9 dB at 16 stages and 14.2 dB at 32 stages. The presented sensor is suitable for application in low illumination, high scanning speed, and remote sensing systems.

A time error mathematical model is proposed to study the impact of nonlinear response and noises on imaging of time-based Pulse Width Modulation (PWM) pixel with the Correlated Double Sampling (CDS). The errors introduced by nonlinearity and certain noises, including fixed pattern noise (FPN), reset noise, shot noise and input-referred noise of pixel-level comparator, are studied. The relative error is impacted not only by the noise voltage, but also the comparator reference voltages, V refh and V refl . In the 0.18 μm CMOS process, the simulation result shows that the noises which have the largest impact on imaging are FPN and shot noise. The higher the V refh and V refl are, the smaller the error is introduced by FPN. The larger the difference between V refh and V refl is, the better the signal-to-noise ratio (SNR) is. The influence of reference voltage and clock frequency on dynamic range, and the trade-off between dynamic range and speed are also analyzed in this paper. Finally, the rules of reference voltage selection are discussed. The results can serve as a guideline to the design of the time-based PWM pixel with CDS.

A 10-bit single-slope analog-to-digital converter (ADC) for time-delay-integration CMOS image sensor was proposed. A programmable ramp generator was applied to accomplish the error calibration and improve the linearity. The ADC was fabricated in a 180 nm 1P4M CMOS process. Experimental results indicate that the differential nonlinearity and integral nonlinearity were 0.51/−0.53 LSB and 0.63/−0.71 LSB, respectively. The sampling rate of the ADC was 32 kHz.

A time error correction method for improving the accuracy of asynchronous CMOS (Complementary Metal Oxide Semiconductor) imager sensor (CIS) is proposed. By adding a time error measurement unit in each pixel, the time error can be recorded, and then is sent out together with the address-events. Besides, in the external processing circuit, the correction will be accomplished before making time-stamping. For the sake of clarifying the influences on the image accuracy, different scale of the pixel array, event collisions, accuracy of time-stamping and illumination are adopted in the simulation. The simulation results of the Matlab Simulink show that, in an 8?×?8 asynchronous CIS without time error correction, when the illumination is 103?~?105 lx, the error of the image accuracy is from 0.4 % to 28 %. With the decrease of the time-stamping accuracy, the expansion of pixel array, the increase of event collisions and the strengthening of illumination, the error would deteriorate further. As to the model of asynchronous CIS with time error correction, when the accuracy of the time-stamping is 10 ns, the time error can be controlled within 20 ns. For the same illumination, the maximal error of image is 0.31 %.

An addition scheme applicable to time-delay integration (TDI) CMOS image sensor is proposed, which adds signals in the charge domain in the pixel array. A two-shared pixel structure adopting two-stage charge transfer is introduced, together with the rolling shutter with an undersampling readout timing. Compared with the conventional TDI addition methods, the proposed scheme can reduce the addition operations by half in the pixel array, which decreases the power consumption of addition circuits outside the pixel array. The timing arrangement and pixel structure are analyzed in detail. The simulation results show that the proposed pixel structure can achieve the charge addition with negligible nonlinearity, therefore the power consumption of the periphery addition circuits can be reduced by half theoretically.

A statistical model based on large sample simulation is established to study the relationship between random telegraph signal (RTS) noise and the number of time delay integration (TDI) stages in TDI CMOS image sensor (CIS). Matlab simulation results show that the mean value of RTS noise increases by a factor greater than M 0.5 when the number of TDI stages is M , and the factor approximates to M 0.5 with larger TDI stages. In noise histogram, RTS noise exhibits Gaussian distribution when the number of TDI stages is more than a special value. These results serve as a guideline for the design of TDI stages and the analysis of noise.

A switched-current sample-and-hold circuit with low charge injection was proposed. To obtain low noise and charge injection, the zero-voltage switching was used to remove the signal-dependent charge injection, and the signal-independent charge injection was reduced by removing the feed-through voltage from the input port of the memory transistor directly. This current sample-and-hold circuit was implemented using CMOS 180 nm 1.8 V technology. For a 0.8 MHz sinusoidal signal input, the simulated signal-to-noise and distortion ratio and total harmonic distortion were improved from 53.74 dB and −51.24 dB to 56.53 dB and −54.36 dB at the sampling rate of 20 MHz respectively, with accuracy of 9.01 bit and power consumption of 0.44 mW.

A new multiple orientation event-based neurobiological recognition system is proposed by integrating recognition and tracking function in this paper, which is used for asynchronous address-event representation (AER) image sensors. The characteristic of this system has been enriched to recognize the objects in multiple orientations with only training samples moving in a single orientation. The system extracts multi-scale and multi-orientation line features inspired by models of the primate visual cortex. An orientation detector based on modified Gaussian blob tracking algorithm is introduced for object tracking and orientation detection. The orientation detector and feature extraction block work in simultaneous mode, without any increase in categorization time. An addresses lookup table (addresses LUT) is also presented to adjust the feature maps by addresses mapping and reordering, and they are categorized in the trained spiking neural network. This recognition system is evaluated with the MNIST dataset which have played important roles in the development of computer vision, and the accuracy is increased owing to the use of both ON and OFF events. AER data acquired by a dynamic vision senses (DVS) are also tested on the system, such as moving digits, pokers, and vehicles. The experimental results show that the proposed system can realize event-based multi-orientation recognition. The work presented in this paper makes a number of contributions to the event-based vision processing system for multi-orientation object recognition. It develops a new tracking-recognition architecture to feedforward categorization system and an address reorder approach to classify multi-orientation objects using event-based data. It provides a new way to recognize multiple orientation objects with only samples in single orientation.

A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper. The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a three-phase column-parallel circuit based on two floating gate inverters and switched-capacitor network. The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step. A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step, which can reduce the clock step from 2 n to 2(n/2+1). The floating gate inverters are implemented to reduce the power consumption. Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter, which can equalize the coupling path in three phases of the proposed circuit. This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18 μm process. Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10 MHz. The power consumption of this circuit is less than 36.5 μW with a 3.3 V power supply. The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.

Polymer-based microfluidic chips are fabricated to demonstrate three-dimensional(3-D) spatial confinement of microspheres and fluids for microsphere single-pass biological applications and fluidic control. In this article, we report a novel fabrication process of a Poly(dimethylsiloxane) (PDMS) device by soft lithography, which involves creation of positive mold containing the sub-20µm width microchannels microstructures that were fabricated by Hot Embossing Lithography(HEL). The microspheres with the diameter of 13~15µm were injected directly into the inlet reservoirs and passed through one by one in the microchannels by the external pumps which has great potential for low-cost and more efficient detection and counting based on microspheres.

A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise (FPN) cancellation is proposed. By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling (CDS), pixel FPN is cancelled and column FPN is stored and eliminated by the sample-and-hold operation of digitally programmable gain amplifier (DPGA). The bandwidth balance technology based on operational amplifier (op-amp) sharing is also introduced to decrease the power dissipation of traditional multi-stage switched capacitor DPGA. The circuit is designed and simulated using 1P6M 0.18 μm 1.8 V/3.3 V process. Simulation results indicate that the proposed CDS scheme can achieve an FPN of less than 1 mV. The total sampling capacitor per column is 0.9 pF and no column-wise power is dissipated. The die area and FPN value are cut by 70% and 41% respectively compared with amplifier-based CDS. The op-amp sharing gain stage can achieve a 12-bit precision and also implement an 8-bit gain controlling within a gain range of 24 dB. Its power consumption is 1.4 mW, which is reduced by 57% compared with traditional schemes. The proposed readout circuit is suitable for the application of low power cost-sensitive imaging systems.

An accurate circuit of PWM/PFM mode converting and a circuit of auto-adaptively adjusting dimension of power transistor are described. The duty cycle of the signal when the control mode converts can be gained accurately by using ratios of currents and capacitances, and an optimal dimension of power transistor is derived with different loads. The converter is designed by 0.35 µm standard CMOS technology. Simulation results indicate that the converter starts work at 0.8 V input voltage. Combined with synchronized rectification, the transfer efficiency is higher than 90% with full load range, and achieves 97.5% at rating output.

An adaptive ramp generator based on linear histogram was proposed for the built-in self-test (BIST) of analog to digital convertor (ADC) in CMOS image sensor. By comparing the generated ramp signal to a reference voltage and feeding back a calibration signal, the slope adjustment was implemented, and high linearity and precision of ramp slope were realized. By modulating the pulse width and reference voltage, sweep length varied from microsecond to second and signal swing could reach 3 V with 5.6 mW power consumption. The ramp was used as input to an ideal 10-bit single-slope ADC, and the corresponding DNL and INL were 0.032 LSB and 0.078 LSB, respectively.

With the further shrinking of IC dimensions, low- material has been widely used to replace the traditional SiO interlayer dielectric (ILD) in order to reduce the interconnect delay. The introduction of low- material into silicon imposed challenges on dicing saw process. ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low- material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300-mm CMOS90-nm dual damascene low- wafer was chosen as a test vehicle to develop a robust low- dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street, etc.) affecting cutting quality were studied and optimized. The selected C90 Dual damascene low- device passed package reliability tests with the optimized low- dicing saw recipe and process. The further improvement and solutions in eliminating the low- dicing saw peeling were also explored.