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10 results on '"Sun, Wei-Tsun"'

1. Validating Static WCET Analysis: A Method and Its Application

Author

Sun, Wei-Tsun, Jenn, Eric, Cassé, Hugues, Centre National de la Recherche Scientifique - CNRS (FRANCE), Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE), Thales (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), IRT Saint Exupéry - Institut de Recherche Technologique (FRANCE), Institut de Recherche en Informatique de Toulouse - IRIT (Toulouse, France), IRT Saint Exupéry - Institut de Recherche Technologique, Thales (France), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, and Université Toulouse III - Paul Sabatier (UT3)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], nML, 000 Computer science, knowledge, general works, Architectures Matérielles, ISS, Validation of WCET tools, Computer Science, Système d'exploitation, Réseaux et télécommunications, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS], Systèmes embarqués
Abstract

International audience; WCET analysis is a key activity in the development of safety critical real-time systems. Whether upper bounds on WCETs are obtained using static analysis or measurements, the confidence on the compliance of a system with its temporal requirements directly depends on the confidence on these estimations. Static WCET analysis based on abstract interpretation takes benefits from its formal foundations. However, it also strongly depends on the correctness of the underlying models. We hereby show how we have validated the version of the data flow static analyser of OTAWA applied to the AURIX TC275 target processor.

Published
2019
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2. Using execution graphs to model a prefetch and write buffers and its application to the Bostan MPPA

Author

Sun, Wei-Tsun, Cassé, Hugues, Rochange, Christine, Rihani, Hamza, Maiza, Claire, SUN, Wei-Tsun, Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), VERIMAG (VERIMAG - IMAG), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
pipeline analysis, static analysis, VLIW, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, Real-Time, WCET, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems
Abstract

International audience; Verifying the temporal properties of critical systems embedded in vehicles, like planes or cars, is crucial to avoid catastrophic issues. A key component of this verification is the Worst Case Execution Time (WCET) of the programs composing these systems. A common and sound approach to compute WCET is based on static analysis of the programs that requires, in turn, to precisely model the behavior and the timings of the hardware. Processor-specific features such as pipelines, caches, and buffers influence the hardware performances significantly. Hence taking processor features into account when estimating WCET is essential. Modeling the processor's features formally to ensure safe and accurate estimation is then a must. In this paper, we present the methodology applied to capture the behavior of prefetch and write buffers of the Kalray Bostan MPPA microprocessor, and to incorporate the established models with the Execution Graph (XG) to obtain WCET estimation. These analyses are then applied to the Mälardalen benchmark suite and the experimentation results validate the feasibility of our approach.

Published
2018

3. Assessing Software Abstractions in WCET Analysis of Reactive Programs

Author

Jahier, Erwan, Halbwachs, Nicolas, Maiza, Claire, Raymond, Pascal, Sun, Wei-Tsun, Cassé, Hugues, Centre National de la Recherche Scientifique (CNRS), Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), VERIMAG (VERIMAG - IMAG), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), Verimag, Université Grenoble Alpes, and ANR-12-INSE-0001,W-SEPT,WCET: SEmantique, Précision, Traçabilité(2012)

Subjects
Static and dynamic program analysis, Environments modeling, [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], Reactive systems, Synchronous languages, WCET Estimation
Abstract

The estimation of the worst case execution time (WCET) of a reactive system on agiven architecture is an important goal for time-critical systems. However, it cannotbe achieved exactly, because of the complexity of modern architectures, the undecidability of most program analysis problems, and the need of taking into accountthe actual environment in which the system is intended to work. As a consequence,two approaches are possible: extensively testing the system with realistic input scenarios (dynamic method) provides an under-approximation of the WCET, while aguaranteed over-approximation can be obtained by applying static analysis of software and hardware. Comparing the results of both approaches and reducing the gapbetween them is interesting to assess the quality of the static analysis, and to decidewhen further refinements are useless. In this paper, we propose a methodology anda combination of tools to assess the result of software static analysis in the case ofreactive programs. In order to permit a meaningful comparison, we perform a dynamic analysis using a cycle accurate simulator based on the same hardware modelas the one used for static analysis. Moreover, we use an existing quite sophisticatedframework to conduct the generation of reactive input scenarios, in order to trackthe worst case. This methodology and the use of associated tools is illustrated on asmall but realistic example.

Published
2018

4. The W-SEPT Project: Towards Semantic-Aware WCET Estimation

Author

Maiza, Claire, Raymond, Pascal, Parent-Vigouroux, Catherine, Bonenfant, Armelle, Carrier, Fabienne, Cassé, Hugues, Cuenot, Philippe, Claraz, Denis, Halbwachs, Nicolas, Jahier, Erwan, Li, Hanbing, de Michiel, Marianne, Mussot, Vincent, Puaut, Isabelle, Rochange, Christine, Rohou, Erven, Ruiz, Jordy, Sotin, Pascal, Sun, Wei-Tsun, VERIMAG (VERIMAG - IMAG), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Continental Automotive France [Toulouse], Pushing Architecture and Compilation for Application Performance (PACAP), Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-ARCHITECTURE (IRISA-D3), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-CentraleSupélec-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), ARCHITECTURE (IRISA-D3), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), ANR-12-INSE-0001,W-SEPT,WCET: SEmantique, Précision, Traçabilité(2012), Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes 1 (UR1), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Toulouse Mind & Brain Institut (TMBI), Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], 000 Computer science, knowledge, general works, Computer Science, 0202 electrical engineering, electronic engineering, information engineering, Program analysis, 020207 software engineering, 02 engineering and technology, Worst-case execution time analysis, Static analysis
Abstract

International audience; Critical embedded systems are generally composed of repetitive tasks that must meet hard timing constraints, such as termination deadlines. Providing an upper bound of the worst-case execution time (WCET) of such tasks at design time is necessary to guarantee the correctness of the system. In static WCET analysis, a main source of over-approximation comes from the complexity of the modern hardware platforms: their timing behavior tends to become more unpredictable because of features like caches, pipeline, branch prediction, etc. Another source of over-approximation comes from the software itself: WCET analysis may consider potential worst-cases executions that are actually infeasible, because of the semantics of the program or because they correspond to unrealistic inputs. The W-SEPT project, for “WCET, Semantics, Precision and Traceability”, has been carried out to study and exploit the influence of program semantics on the WCET estimation. This paper presents the results of this project : a semantic-aware WCET estimation workflow for high-level designed systems.

Published
2017
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5. Dynamic Branch Resolution based on Combined Static Analyses

Author

Sun, Wei-Tsun, Cassé, Hugues, Institut National Polytechnique de Toulouse - INPT (FRANCE), Centre National de la Recherche Scientifique - CNRS (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), and Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], 000 Computer science, knowledge, general works, Dynamic branch, Assembly, Système d'exploitation, Réseaux et télécommunications, Static analysis, Systèmes embarqués, Machine language, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], Architectures Matérielles, Computer Science, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS], WCET
Abstract

International audience; Static analysis requires the full knowledge of the overall program structure. The structure of a program can be represented by a Control Flow Graph (CFG) where vertices are basic blocks (BB) and edges represent the control flow between the BB. To construct a full CFG, all the BB as well as all of their possible targets addresses must be found. In this paper, we present a method to resolve dynamic branches, that identifies the target addresses of BB created due to the switch-cases and calls on function pointers. We also implemented a slicing method to speed up the overall analysis which makes our approach applicable on large and realistic real-time programs.

Published
2016

10. LibGALS.

Author

Sun, Wei-Tsun, Salcic, Zoran, and Malik, Avinash

Published
2010

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