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We investigate in detail the influence of AlN passivation on dynamic ON-resistance ( \(R_{\mathrm{{\scriptstyle ON}}}\) ) and electric field ( \(E\) -field) distribution in high-voltage AlGaN/GaN high electron mobility transistors (HEMTs) on a Si substrate based on pulsed \(I\) – \(V\) measurements, electroluminescence (EL) microscopy, and 2-D physics-based numerical device simulations. It is found that the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) increase has been significantly suppressed to below 10% at various temperatures ranging from −50 to 200 °C owing to the effective and robust compensation of deep acceptor-like trap states at the AlN/GaN (passivation/cap) interface by the additional positive polarization charges induced in the epitaxial AlN thin passivation layer grown in a plasma-enhanced atomic layer deposition system. To the best of our knowledge, this is the first time that highly suppressed current collapse in an AlGaN/GaN HEMT on a Si substrate within a wide temperature range is ever reported. By monitoring the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) for 100 consecutive 133-kHz switching cycles, its variation is observed to be less than 2.5%, indicating excellent stability of the passivation effectiveness. The electric field in an AlN-passivated device is found to be well confined at the drain-side gate edge, as shown in EL measurement and numerical simulation results. This phenomenon directly suggests that the virtual gate effect arising from surface trap charging has been effectively alleviated by the AlN passivation technique. [ABSTRACT FROM AUTHOR]

We experimentally demonstrate a high-voltage low-standby power startup circuit for powering up the off-line switched-mode power supply (SMPS) during the startup period by exploiting monolithically integrated enhancement/depletion-mode metal–insulator–semiconductor high electron mobility transistors (E/D-mode MIS-HEMTs) fabricated on a GaN-on-Si power device platform. The E/D-mode MIS-HEMTs exhibit a threshold voltage of +1.2 and -11~V, respectively. The high-voltage D-mode device used in the demonstration features an OFF-state breakdown voltage of 640 V and a safe operating area with a thermal limitation of 11.6 W/mm, whereas the low-voltage E-mode device features a source-gate breakdown voltage of 98 V, satisfying the requirement of the startup circuit. The functionality of the startup circuit is successfully achieved with an input voltage range 10–200 V and a startup current of 1.08 mA. [ABSTRACT FROM AUTHOR]

The effects of interface oxidation on the transport behavior of the 2-D electron gas (2DEG) in AlGaN/GaN heterostructures by plasma-enhanced-atomic-layer-deposited AlN (PEALD-AlN) passivation were investigated using temperature-dependent Hall-effect and X-ray photoelectron spectroscopy (XPS) characterizations. AlGaN/GaN heterostructure with a 4-nm-thick PEALD-AlN passivation exhibits good 2DEG transport behavior and stability at moderately high temperature (e.g., 275 °C). However, serious oxidation of the AlN/GaN (cap layer) interface occurs as the sample is heated up to 400 °C in low-pressure atmosphere, as verified by an increased Ga-O bond in Ga 3d core-level spectra. The oxidation leads to a significant reduction of 2.47 × 1012 cm-2 in the 2DEG density in the channel. A modified AlN passivation structure with Al2O3/AlN (10/4 nm) stack is shown to be able to effectively suppress the oxidation of the AlN/GaN interface, demonstrating an enhanced 2DEG density and high-temperature stability even when the sample is heated up to 500 °C. Based on XPS and 2DEG recovery experiments, it is suggested that acceptor-like deep levels have been generated in the near-surface region of AlGaN/GaN heterostructure because of the oxidation, and trapping of these deep levels results in significant depletion of the 2DEG in the channel. The effects of PEALD-AlN passivation on the strain in the AlGaN barrier of AlGaN/GaN heterostructures are also evaluated with high-resolution X-ray diffraction technique. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the problem of detecting a multichannel signal in nonhomogeneous environment. The nonhomogeneity is assumed to be caused by the generalized eigenrelation (GER). According to three common detector design criteria, namely, the generalized likelihood ratio (GLRT), Rao test, and Wald test, we derive three adaptive detectors, which are the generalizations of the existing ones. Numerical examples show that the detection performance of the detectors are significantly affected by the GER structure nonhomogeneity. Moreover, the GLRT provides better detection performance than the other two detectors. [ABSTRACT FROM AUTHOR]

Effective interface engineering techniques in III-nitride heterojunction power devices, aiming at yielding high VTH stability in insulated-gate devices and suppressed current collapse in high-voltage switching operation, are of critical significance to enhance device performance and reliability. In this work, we present an interface enhancement technology featuring in situ low-damage NH3/Ar/N2 pre-gate plasma treatment prior to the ALD-Al2O3 deposition for high-performance III-nitride MIS-HEMTs. It is manifest that this technology can effectively remove the native oxide while forming a monocrystal-like nitridation interfacial-layer (NIL) on the III-nitride surface. The Al2O3(NIL)/GaN/AlGaN/GaN MIS-heterostructures with high-quality interface exhibit well-behaved electrical characteristics, including a small subthreshold swing of ∼64 mV/dec, a small hysteresis of ∼0.09 V, tiny f/T dispersions in the C- V characteristics, and low interface trap density of ∼1 × 1012-6 × 1012 cm−2eV−1. Cross-sectional TEM micrograph of the Al2O3/III-nitride gate stack with a monocrystal-like nitridation interfacial-layer (NIL). [ABSTRACT FROM AUTHOR]

In this paper, a surface potential-based terminal charge and capacitance model, including parasitic components for AlGaN/GaN HEMTs is developed. First, by solving the charge control equations, the sheet charge density in the channel is modeled with a close-form expression. Then, using this result, based on the surface potential definition, the intrinsic terminal charges and capacitances are derived consistently with current model. Finally, by introducing parasitic components, the capacitances for the full structure of the HEMT devices are given. The model is evaluated step-by-step with good agreements compared with the TCAD simulations and the experimental data. Meanwhile, the effects of bulk traps and surface traps in the capacitances are analyzed. The complete model, including currents and capacitances has been implemented in i-MOS platform for evaluations and circuit simulations. [ABSTRACT FROM PUBLISHER]

Wide bandgap III‐nitride (III‐N) power switching transistors are capable of delivering superior performance for next‐generation energy‐efficient and compact power conversion systems. Owing to suppressed gate leakage and enlarged gate swing, III‐N insulatedgate devices are highly preferred over the conventional Schottkygate counterparts for high‐voltage power switches. Meanwhile, surface passivation with dielectric deposited in the gate–drain access region is necessary to allievate the surface‐state induced current collapse in high‐voltage switching operation. Therefore, effective interface engineering techniques for III‐N devices are of critical significance to enhance threshold‐voltage stability and dynamic performance. Chen et al. (pp. 1059–1065) present an interface enhancement technology featuring in situ low‐damage NH3/Ar/N2 pre‐gate plasma treatment prior to the Al2O3 gatedielectric deposition. This technology can effectively remove the native oxide while forming a monocrystal‐like nitridation interfaciallayer (NIL) with Al–N bonds on the III‐N surface, enabling the realization of high‐performance and high‐stability III‐N insulatedgate devices. The Al2O3(NIL)/GaN/AlGaN/GaN MIS heterostructures with high‐quality interface exhibit record electrical characteristics, including a steep subthreshold swing of ∼64 mV/dec, a small hysteresis of ∼0.09 V, tiny f/T‐dispersions in the capacitance– voltage characteristics, and low interface trap density. [To honour the laureates of the Nobel Prize in Physics 2014, the cover of this pss (a) issue shows a specially designed pss logo assembled from blue nitride LEDs (courtesy of Armin Dadgar, Technical University of Magdeburg)]. [ABSTRACT FROM AUTHOR]

Al2O3–AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) featuring indium tin oxide transparent gate electrode are fabricated for the purpose of evaluating the gate reliability. The transparent gate electrode allows electroluminescence (EL) observation in the region directly under the gate, which cannot be performed in conventional MIS-HEMTs with opaque gate electrode. Normally OFF transparent-gate MIS-HEMTs were realized by implanting fluorine ions into the AlGaN barrier prior to the deposition of Al2O3. The dependence of EL on bias condition was investigated with the color of EL resolved by filters. Gate dielectric degradation in MIS-HEMTs was induced by OFF state drain-bias stress, as detected by the increased gate leakage current. Location of the gate degradation could be clearly identified by EL imaging through the transparent gate. From the EL image, the passivation layer under the overhang of T-shaped gate is found to be vulnerable to OFF-state stress, which is confirmed by simulation. [ABSTRACT FROM AUTHOR]

The GaN-to-Si vertical conduction mechanisms on a low resistivity p-type (111) Si substrate under high-voltage operation are investigated using the temperature-dependent high-voltage C-V characterization and device simulation. It is found the deep depletion and weak inversion in Si will result in a high electric field at the GaN/Si interface and induce the impact ionization of Si. The generated electrons will be injected into GaN buffer layer, fill in buffer traps and act as free carriers in GaN, eventually leading to considerable vertical leakage in the AlGaN/GaN-on-Si structures. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

The threshold voltage ( VT) instability of metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) is investigated. In the enhancement-mode AlGaN/GaN MIS-HEMT fabricated by fluorine plasma implantation technique featuring Al2O3 gate dielectric, a hysteresis of 0.6 V in transfer characteristics is observed by quasi-static I - V (current-voltage) measurement, in which the gate bias is swept at a low rate (0.7 V/s). Pulsed transfer characteristics measurement, however, unveils much larger hysteresis under the same gate voltage swing. The VT-instability is attributed to the traps located at the dielectric/III-nitride interface as well as in the bulk of gate dielectric. It is proposed that pulsed measurement can count for the effect of fast traps (shallow traps) while the quasi-static measurement can only reflect slow traps (deep traps), and is more accurate for VT-instability evaluation. In addition, the existence of bulk traps is implied by a slow time-dependent shift of VT under large gate bias. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]