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The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractors and their contributions are not well understood. One of the key challenges in FAV integration is the need to create of topography which can be either achieved by recessing the metal lines or by selective insulator deposition. Wet recess process has been promising for enabling downstream integration learning of conformal cap deposition, ultra low-k gap-fill, and via landing on recessed area. In this paper wet recess challenges for topography creation and key process improvements that improve the resistance distribution are discussed.

The impact of cohesive forces in ruthenium (Ru) is studied for tighter interconnect technologies; such forces can result in bending of lines at these pitches. The sensitivity of these forces to process variations such as aspect ratio of lines, trench profiles, and critical dimensions are studied. It is observed that lower aspect ratio and higher dielectric modulus alleviate the effects of these cohesive forces. An ab-initio molecular dynamics model is used to compare behavior of Ru with that of copper. Higher surface energy of Ru potentially contributes to this bending phenomenon.

It has been confirmed that Co diffusion from the cap into a Ru liner (resulting in Co depletion at the top of Cu lines) is the root cause of EM degradation for Cu interconnects in the case of using a combination of Ru liner and selective Co cap. Increasing the Co cap thickness is an effective EM degradation remedy, but at the expense of Vbd degradation (breakdown voltage between lines) due to lateral growth of Co. Alternatively, replacing the Co cap with a Ru cap showed marginal EM improvement. Here we report a novel Co-doped Ru liner, which demonstrates a significant EM performance boost by addressing the Co diffusion issue. This Co-doped Ru liner is shown to be a promising liner of choice for Cu interconnects in advanced nodes.

Self-Aligned Multiple Patterning is one of the multiple-patterning techniques to realize sub optical lithography technology nodes. The challenges for advanced interconnect levels with multiple-patterning integration are to control both metal CD and the space between line ends. This can be associated with complicated process integration. In this paper, a novel patterning scheme, metal on metal multiple patterning integration, which significantly simplified the process steps and enabled self-aligned block (SAB), is demonstrated for a single damascene level by process emulation. This novel integration utilizes metal as the mandrel. In addition to that, in this scheme the non-mandrel metal material could be different from the mandrel metal. As a result, mandrel metal could have different electrical or physical properties than the non-mandrel metal. As an example, the mandrel metal could have better reliability to carry large current while the non-mandrel could have lower resistivity for performance.

We present a combined experimental and theoretical study of via resistance modulation in Cu interconnects with ultra-scaled diffusion barriers and wetting layers. In particular, we demonstrate that reducing the thickness of the TaN-based diffusion barrier below 1 nm results in a decrease in the measured via resistance, while reducing the thickness of the Co wetting layer below 1 nm has virtually no impact on via resistance. These results are explained using first-principles transport calculations, which show that a 1 nm thick TaN layer is more effective in blocking electrons than a 1 nm thick Co layer. Measurements of time-dependent dielectric breakdown indicate that scaling either TaN or Co layers below 1 nm in thickness results in degraded reliability. These results suggest that there is minimal value in scaling the thickness of Co wetting layers below 1 nm, while scaling TaN diffusion barriers below 1 nm results in a trade-off between performance and reliability.

The impacts of ruthenium and cobalt liners on copper resistivity have been investigated at beyond 7nm dimensions. Liner metal conduction was carefully evaluated in a Cu resistivity derivation using the temperature coefficient of resistivity (TCR) approach. Cu resistivity with Ru liner is higher than with a Co liner by 10-15%, which is verified by RC plot. The resistivity difference is attributed to interface scattering and possibly grain boundary scattering. Interface ab initio calculations show 3-7% increase of Cu resistivity from Co liner to Ru liner.

SADP are one of the important patterning techniques for all the FEOL/BEOL levels in 7 nm technology node and beyond. In BEOL, not only the minimum features, but wide lines are also important for power distribution even in the thin wire levels. However, in the conventional SADP integration, insertion of wide features in the sea-of-wires area cannot be achieved easily. In this paper, various strategies are presented for creating merge features in SADP/SAQP integration. Firstly, using an add on lithography, the mandrel can be selectively merge or remove before the spacer deposition, as a result, merged mandrels or non-mandrels without touching others are created. On the other hand, a spacer cut lithography can be applied after the mandrel pull, then, there is a freedom to cut the spacer between the select features that will merge all the features in the area. Nevertheless, the undesired connections can be cut off by adding one more block-lithography. Therefore, it is possible to create any arbitrary shapes with this technique. The last block-lithography can also be eliminated by introducing pre-defined cuts in the mandrel cut or non-mandrel cut step.

For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm and beyond. Our study suggests promise of this last scheme to meet requirements in line R and EM reliability.

36 nm pitch dual damascene interconnects are patterned and filled with ruthenium. Different adhesion layers are used to form the Ru interconnects. Ru line resistivity is measured by the temperature coefficient of resistivity method, and the area verified by TEM. Ru line resistivity is found to depend on the adhesion layer. The adhesion layers with higher intrinsic resistivities reduced the Ru line resistivity. A ∼10% Ru resistivity reduction can be achieved with ALD TaN or TiN adhesion layers or oxidized TaN, relative to PVD TaN. Grain boundary scattering may play an additional role, as demonstrated by different aspect ratio samples. The lowest Ru resistivity in these interconnects is 15 µΩ-cm, at a cross-sectional area of 300 nm2. Ru damascene metallization is extendible to features with critical dimension around 10 nm. Ru may match Cu line resistance for line dimensions below ∼17 nm.

In this paper, a strategy of performing segment removal in an SAQP (self-aligned quadruple patterning) and its implication on interconnect parasitic capacitance are reported. In order to reduce the cost and process complexity, through process emulations, this study specifically focuses on not introducing additional lithography step(s) or material to the conventional SADP (self-aligned double patterning) integration. Four SAQP process integrations are demonstrated to selectively remove dummy lines in between the signal lines from sea of lines, as a result, the line to line capacitance can be reduced. The conventional non-mandrel block lithography step will only remove every other line. Typically, to remove more lines requires an additional hard mask layer and a first non-mandrel block lithography step where the line to line capacitance can be further reduced. However, in this study, a double spacer transfer scheme is proposed to achieve the same final structure but without the additional hard mask layer and lithography step. Therefore, this could be another option for 7 nm or 5 nm process integration of BEOL interconnects.

Electromigration and resistivity of Cu, Co and Ru on-chip interconnection have been investigated. A similar resistivity size effect increase was observed in Cu, Co, and Ru. The effect of liners and cap, e.g. Ta, Co, Ru and SiC x N y H z , on Cu/interface resistivity was not found to be significant. Multilevel Cu, Co or Ru back-end-of-line interconnects were fabricated using 10 nm node technology wafer processing steps. EM in 22 nm to 88 nm wide Co lines, 24 nm wide Cu with and without a thin Co cap and 24 nm wide Ru lines were tested. These data showed that Cu with a Co cap, Co and Ru had highly reliable EM, although Ru was better than Co and Co was better Cu. The electromigration activation energies for Cu with Co cap and Co were found to be 1.5–1.6 eV and 2.1–2.7 eV, respectively.

Microstructure variation with post-patterning dielectric aspect ratio (AR) and post-plating annealing temperature has been investigated in Cu narrow wires. As compared to the conventional annealing at 100 ◦C for a feature AR of 2.6, both elevated temperature anneals and reduced AR structures modulated Cu microstructure, which then resulted in a reduced rate of electrical resistivity increase with area scaling and an increased electromigration resistance in the Cu narrow wires.

In this paper, the impact of gap-fill planarity on Multi-Self-Aligned Block, SADP (self-aligned double patterning) process for advanced optical technology nodes (7 nm/5 nm) interconnects was studied through process emulations. This study specifically focuses on the insertion of an etch stop layer (ESL) between two coatings of organic planarization layer (OPL), referred to as the tri-layer PM (pattern mask), which enables a thinner OPL for pattern transfer while adding topography correction for non-mandrel block patterning processes. This scheme reduces pillar aspect ratio for improved CD control and flop-over mitigation, as well as topography correction to mitigation false metal patterns in field regions. However, ESL could cause CD variation if it was deposited on the sidewall of spacer where it is a function of the conformality of ESL deposition.

In the attempts to push the resolution limits of 193nm immersion lithography, this work demonstrates the building of 3 metal level 56nm pitch copper dual-damascene interconnects, using Negative-Tone Development Lithography-Etch-Lithography-Etch (LELE) Patterning at line level. Line Resistance and intra-level capacitance can be affected by the double patterning integration, but a good process window has been demonstrated, showing no impact on RC performance. The introduction of a self-aligned via (SAV) process with a TiN hard-mask is able to provide a robust process window in terms of via-metal short yield at line and via level. SAV implementation at these dimensions also affects the aspect-ratio of the structures and leads to new challenges in metallization: optimized profile, without bowing or undercut, is mandatory to enable the filling of 28nm lines. The metal hard-mask has to be removed or at least faceted by erosion. This can be achieved by conventional RIE process optimization, but pushes the RIE selectivity to challenging limits. Physical dimensions on target and via chain yield have been demonstrated by fine tuning RIE process. Profile improvement can also be achieved by the introduction of new WET process, helping the removal of the metal hard-mask while being neutral to the ULK. We have demonstrated good yield and reliability with an integration using hard-mask wet removal.

Integration of high porosity low-k dielectrics faces major challenges as the porosity weakens the dielectric, resulting in severe plasma induced damage (PID) and difficulties in profile control. Post porosity plasma protection (P4) integration strategy addresses those challenges by strengthening the dielectric via porosity refill during the integration steps. Realization of P4 integration at an advanced node is nontrivial. In this paper, we demonstrate the feasibility of the P4 integration scheme in a dual damascene double patterning 48 nm pitch test vehicle with a plasma enhanced chemical vapor deposited (PECVD) k = 2.4 inter-layer dielectric (ILD). In addition, initial results of applying P4 with a PECVD k = 2.2 ILD show promise in reducing capacitance at 48 nm pitch and beyond.

48 nm pitch dual damascene interconnects are patterned and filled with ruthenium. Ru interconnect has comparable high yield for line and via macros. Electrical results show minimal impact for via resistance and around 2 times higher line resistance. Resistivity and cross section area of Ru interconnects are measured by temperature coefficient of resistivity method and the area was verified by TEM. Reliability results show non-failure in electromigration and longer time dependent dielectric breakdown. Based on the data collected, Ru could be a metallization contender at linewidth of 16 nm and below.

We characterize integrated dual damascene Co and Cu BEOL lines and vias, at 10 nm node dimensions. The Co to Cu line resistance ratios for 24 nm and 220 nm wide lines were 2.1 and 3.5, respectively. The Co via resistance was just 1.7 times that of Cu, with the smaller ratio attributed to the barrier layer series via resistance. Electrical continuity of Co via chain structures was good, while some chain-chain shorts and leakage suggests metal residuals from the Co polish process. The Co lines and vias, fabricated using conventional BEOL processes, exhibit good Co fill by TEM, with no visible evidence of Co in the dielectric. The relatively smaller resistance increase for Co vias suggests a potential via resistance benefit, a thinner or less resistive barrier can be employed. Co line resistance will likely not be competitive with Cu until after the next technology node.

Adhesion tests, parametric measurements, and reliability evaluations of an in-situ pre-liner dielectric nitridation process prior to pure Ta liner deposition were carried out, to evaluate the feasibility of reducing via resistance in BEOL Cu/low-k interconnects. Replacing TaN/Ta with Ta in the conventional liner stack reduces Cu via resistance, while the nitridation treatment maintains Cu interconnect integrity and reliability.

A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.

Multi-layer SiNO barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCN and SiN barrier films used at previous technology nodes. Combining SiCN with multi-layer SiNO barrier film provides robust Cu and O barrier properties at film thickness of ∼10–14 nm. SiNO layers in the bi-layer film help lower the dielectric constant and hence provide capacitance benefit in the integrated structures. The high breakdown SiNO layers provide benefit in the via chamfer region and improves inter-level time dependent dielectric breakdown (TDDB). Overall, the SiCN/SiNO bilayer dielectric film shows robust device reliability as compared to the state of the art barrier films.

The Cu line resistance has been observed to reduce after processing through higher interconnect levels. In this paper, the geometry impact on the reduction of Cu interconnect wire resistance was studied on a large data set using data mining techniques. The data show that the narrower and higher the Cu lines, the larger the line resistance reduction and that Cu line height has much stronger impact on resistance reduction than line width.

Effects of Cu surface treatment (NH"3 plasma irradiation) before the cap dielectric deposition on low-k surface damage and Cu surface cleaning were systematically investigated. From the blanket film surface damage evaluations of porous low-k film with high carbon content and the oxygen removal on blanket Cu film after chemical mechanical polishing (CMP), the optimized NH"3 plasma condition such as high RF power and high pressure exhibited the high efficiency for oxygen removal from the Cu surface without increasing the k-value of low-k film. The low-k/Cu interconnect (line/space=40/40nm) for 22nm-node with the high plasma resistant low-k film and the optimized Cu surface treatment showed longer electro-migration lifetime without large degradation of RC performance.

An improvement in interconnect performance implies a reduction of the resistance-capacitance (RC) time constant. Instead of scaling the capacitance at each technology node through a reduction in the dielectric constant of the interlayer dielectric (ILD), the interconnect aspect ratios could be scaled holding the ILD fixed. In this case, the material properties of the ILD must be robust to process-induced damage and amenable to the creation of high aspect ratio features. In addition, a metallization scheme that can provide void free Cu fill in high aspect ratio features is required. Characterization, patterning, and integration results collected on such an ultra-low-k (ULK) ILD material and void free metallization is presented. A measured reduction in the resistance of a 22nm node interconnect in this ILD was observed as a function of increasing aspect ratio. The copper seed deposition process, capable of enabling the fill of even higher aspect ratio features, is also discussed.

Introduction A porous low-k film has been introduced to reduce the interconnect capacitance as the LSI generation progress [1-2]. Since the porous low-k film has larger porosity and higher carbon content than conventional rigid films, its surface is easily damaged by processes during integration. The damage layer has lower carbon concentration and hydrophilic properties, so the moisture uptakes in it [3]. The moisture uptake into porous low-k film causes the line capacitance increase [4]. In this work, we investigated the moisture uptake impact on line capacitance and leakage current in the triple layer interconnect structure. We also estimated dielectric constant of damage layer with including moisture by the capacitance simulation. The moisture control in the damage layer in porous low-k film is very important to reduce the line capacitance and improve the line leakage current as well as damage layer reduction.

We present a combined theoretical and experimental study on the electron transport characteristics across several representative interface structures found in back-end-of-line interconnect stacks for advanced semiconductor manufacturing: Cu/Ta(N)/Co/Cu and Cu/Ta(N)/Ru/Cu. In particular, we evaluate the impact of replacing a thin TaN barrier with Ta while considering both Co and Ru as wetting layers. Both theory and experiment indicate a pronounced reduction in vertical resistance when replacing TaN with Ta, regardless of whether a Co or Ru wetting layer is used. This indicates that a significant portion of the total vertical resistance is determined by electron scattering at the Cu/Ta(N) interface. The electronic structure of these nano-sized interconnects is analyzed in terms of the atom-resolved projected density of states and k-resolved transmission spectra at the Fermi level. This work further develops a fundamental understanding of electron transport and material characteristics in nano-sized interconnects.

In agreement with the ITRS roadmap, there have been several publications supporting the reduction in critical dimensions and the introduction of new materials to semiconductor processing (1,2,3). This paper highlights the observations and solutions to some of the critical material and process interactions encountered during the integration of the back end of line interconnect.

Through-Co self-forming-barrier (tCoSFB) metallization scheme is introduced, with Cu gap-fill capability down to 7 nm-node dimensions. Mn atoms from doped-seedlayer diffuse through CVD-Co wetting layer, to form TaMn O barrier, with integrity proven by vertical-trench triangular-voltage-sweep and barrier-oxidation tests. tCoSFB scheme enables 32% and 45% lower line and via resistance, respectively at 10 nm node dimensions, while achieving superior EM performance to competitive TaN/Co and TaN/Ru-based barriers.

A cost effective 28nm CMOS Interconnect technology is presented for 28nm node high performance and low power applications. Full entitlement of ultra low-k (ULK) inter-level dielectric is enabled. Copper wiring levels can be combined up to a total of 11 levels. The inter-level dielectric was optimized for low k-value and high strength. The feature profiles were optimized to enable defect-free metallization using conventional tools and processes. High yields and robust reliability were demonstrated.

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um 2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

In order to maximize Cu volume and reduce via resistance, barrier thickness reduction is a strong option. Alternative barriers for next-generation BEOL were evaluated in terms of barrier performance to O 2 and Cu diffusion, and effects on reliability. A clear correlation of O 2 barrier performance to electromigration was observed, suggesting that the key role of the barrier layer is to prevent oxidation of Cu or the Cu/barrier interface. Long-throw PVD-TaN showed superior O 2 barrier performance to alternative metals such as PEALD-TaN, thermal ALD-TaN, -TaN(Mn) and - MnN and MnSiO3 self-forming barrier.

In this paper, optimization of 1X BEOL wiring level of 7 nm node is presented. We focus on the interconnect delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on the characteristics of the 10 nm driver circuit. Then the result is compared with a shrunk version of the circuit at the 7 nm dimension. Therefore, the impact of the BEOL on the circuit performance can be determined. The interconnect delay is plotted as a function of wire resistance, via resistance and capacitance. In order to better optimize the BEOL architecture, contour plots of resistance versus capacitance are presented in this paper. The result of this paper is indicating a strong dependency of circuit performance on the wiring length which is a new challenge. Optimization of BEOL architecture therefore requires a new approach which is outlined in this paper. As a result, we would like to bring this to the design community's attention.

In studying integrated dual damascene hardware at 10 nm node dimensions, we identified the mechanism for Co liner enhancement of Cu gap-fill to be a wetting improvement of the PVD Cu seed, rather than a local nucleation enhancement for Cu plating. We then show that Co “divot” (top-comer slit void defect) formation can be suppressed by a new wet chemistry, in turn eliminating divot-induced EM degradation. Further, we confirm a relative decrease in Cu-alloy seed proportional resistivity impact compared to scattering at scaled dimensions, and finally we address the incompatibility between the commonly-used carbonyl-based CVD-Co process with Cu-alloy seed EM performance This problem is due to oxidation of Ta(N) barriers at the TaN/CVD-Co interface by carbonyl-based CVD processes, which then consumes alloy atoms before they can segregate at the Cu/cap interface. We show that O-free CVD-Co may solve this problem. The above solutions may then enable CVD-Co/Cu-alloy seed integration in advanced nodes.

For sub-64nm pitch interconnects build, it is beneficial to use Self Aligned Double Patterning (SADP) scheme for line level patterning. Usually a 2X pitch pattern was printed first, followed by a Sidewall Image Transfer (SIT) technique to create the 1X pitch pattern. A block lithography process is then used to trim this pattern to form the actual designed pattern. In this paper, 48nm and 45nm pitch SADP build will be used as examples to demonstrate the SADP patterning scheme. General discussions about this patterning scheme will be provided including: 1) the process flow of this technique, 2) benefits of the technique vs. pitch split approach, 3) the design impact and limitation, and 4) the extendability to smaller line pitch build.

Cu(Mn) alloy seed BEOL studies revealed fundamental insights into Mn segregation and EM enhancement. We found a metallic-state Mn-rich Cu layer under the MnOx layer at the Cu/SiCNH cap interface, and correlated this metallic layer with additional EM enhancement. A carbonyl-based CVD-Co liner film consumed Mn, reducing its segregation and EM benefit, suggesting O-free Co liner films are strategic for Cu-alloy seed extendibility.

This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.

Critical parameters of low-k films were defined to keep capacitance benefit and TDDB reliability in the scaling BEOL module, according to various analyses. In order to meet the criteria of high carbon content, low porosity with small pores, and high adhesion strength with less adhesion layer, precursor and process were designed for the SiOCH with k∼2.5. The benefits in integration and reliability from the newly developed robust low-k film were verified through the trench-first integration of 80 nm-pitch BEOL modules.

Three metal level 56nm-pitch Cu dual damascene interconnects in k2.7 low-k ILD have been demonstrated by using sidewall-image-transfer (SIT) patterning scheme to investigate the feasibility of the SIT process for sub 50nm-pitch technology node. 45nm-pitch line resistance (R) and capacitance (C) simulation are performed to estimate the R-C variation for double patterning schemes. The photoresist mandrel SIT process for 56nm-pitch Cu line is investigated to develop the constant line pitch and less line edge roughness (LER). The basic electrical properties such as line open/short and via chain open/short yields are ∼100%. The 56nm-pitch R-C variation is comparable to simulated 80nm-pitch R-C variation. The SIT patterning process is a strong candidate to improve the R-C variation for sub50nm-pitch technology nodes.

The objective of this work is to describe the advances in 193nm photoresists using negative tone developer and key challenges associated with 20nm and beyond technology nodes. Unlike positive tone resists which use protected polymer as the etch block, negative tone developer resists must adhere to a substrate with a deprotected polymer matrix; this poses adhesion and bonding challenges for this new patterning technology. This problem can be addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in them (SiARC), which are specifically tailored for compatibility with the solvent developing resist. We characterized these modified SiARC materials and found improvement in pattern collapse thru-pitches down to 100nm. Fundamental studies were carried out to understand the interactions between the resist materials and the developers. Different types of developers were evaluated and the best candidate was down selected for contact holes and line space applications. The negative tone developer proximity behavior has been investigated through optical proximity correction (OPC) verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to less than 100 adders/wafer by optimizing the develop process. Electric yield test has been conducted and compared between positive tone and negative tone developer strategies. In addition, we have done extensive experimental work to reduce negative tone developer volume per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of positive tone CoO.

A self-aligned via(SAV) process was employed to build 64nm pitch Dual-Damascene(DD) interconnects using a pitch split double exposure pattering scheme to form the Cu lines. TiN hardmask (HM) density and thickness were optimized to achieve the SAV process and DD structure build. We present STEM cross sections of the structures after TiN HM deposition, HM open and DD RIE to determine the minimum required TiN HM thickness for the SAV process. We characterized the TiN loss for each RIE step from cross section results and defined the optimal TiN thickness for 64nm pitch interconnects. Using the optimized TiN thickness, we fabricated DD structures and compared the metal-to-via short electrical performance for SAV and non-SAV processes to show the overlay (OL) impact on shorts yield. Structures fabricated using the SAV process have excellent yield regardless of the degree of via misalignment in the SAV direction since no via CD growth occurs in the constrained SAV direction, while those processed with a non-SAV scheme show via yield degradation with increasing via misalignment. Also, with respect to misalignment in the non-SAV direction, there were no significant electrical differences between structures made using SAV and non-SAV approaches.

A CVD-hybrid dielectric/metal liner has been demonstrated by simulation and actual structure. From line resistance (R) and line capacitance (C) simulation, the CVD-hybrid liner deposited on porous ULK (k=2.2) inter layer dielectrics (ILD) is shown that it is possible to improve RC performance. The CVD-hybrid liner with CVD-SiCN and CVD-Ru shows good liner conformality, Cu diffusion barrier property and oxidation barrier property. Integration process is investigated to achieve optimum CVD-hybrid liner structure with special RIE technique. 14.6% RC performance improvement can be achieved with triple-layered ULK(k=2.2)/Cu integrated interconnect structure. The CVD-hybrid liner is a strong candidate to achieve a better RC performance for future technology nodes.

This work demonstrates the building of 64 nm pitch copper single and dual damascene interconnects using pitch split double patterning scheme to enable sub 80nm pitch patterning. A self-aligned-via (SAV) litho/RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. An undercut free post RIE trench profile enabled the good metal fill. Initial reliability test result and the possibility of using the same scheme for 56 nm pitch interconnects are also discussed.

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

A 32 nm BEOL with PVD CuMn seedlayer and conventional PVD-TaN/Ta liner was fully characterized by fundamental, integrated, and reliability methods. CuMn was confirmed to have fundamental advantages over CuAl, such as higher electromigration (EM) reliability for the same Cu line resistance (R). Both low R and high reliability (EM, SM, and TDDB) were achieved. Improved extendibility of CuMn relative to CuAl was also supported by studies of alloy interactions with advanced liner materials Ru and Co, and by enhancement of ultra-thin TaN barrier performance.

Fundamental material interactions as pertinent to nano-scale copper interconnects were studied for CVD Co with a variety of micro-analytical techniques. Native Co oxide grew rapidly within a few hours (XPS). Incorporation of oxygen and carbon in the CVD Co films (by AES and SIMS) depended on underlying materials, such as Ta, TaN, or Ru. Copper film texture (by XRD) and agglomeration resistance (by AFM) showed correlations with amounts of in-film oxygen/carbon. Cobalt diffused through copper at normal processing temperatures (by SIMS). CVD Co demonstrated diffusion barrier performance to Cu (by Triangular Voltage Sweep, TVS), but not to O 2 . CVD Co was applied to 32 nm/22 nm damascene Cu interconnect fabrication in a scheme defined by the material studies. Lower post-CMP defect density and longer electromigration lifetimes were obtained.

In this paper, we wish to report, for the first time, on a simple, low-cost, novel way to form dual-damascene copper (Cu) on-chip interconnect or Back-End-Of-the-Line (BEOL) structures using a patternable low dielectric constant (low-κ) dielectric material concept. A patternable low-κ dielectric material combines the functions of a traditional resist and a dielectric material into one single material. It acts as a traditional resist during patterning and is subsequently converted to a low-κ dielectric material during a post-patterning curing process. No sacrificial materials (separate resists or hardmasks) and their related deposition, pattern transfer (etch) and removal (strip) are required to form dual-damascene BEOL patterns. We have successfully demonstrated multi-level dual-damascene integration of a novel patternable low-κ dielectric material into advanced Cu BEOL. This κ=2.7 patternable low-κ material is based on the industry standard SiCOH-based (silsesquioxane polymer) material platform and is compatible with 248 nm optical lithography. Multilevel integration of this patternable low-κ material at 45 nm node Cu BEOL fatwire levels has been demonstrated with very high electrical yields using the current manufacturing infrastructure.