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For real-time applications such as autonomous driving and virtual reality (VR), we previously proposed an ultra-low-latency video coding method, which adopts line-based processing for Full-HD video. In this paper, we newly propose a design and implementation of the ultra-low-latency video encoder. In order to reduce the hardware amount, image-prediction specification is optimized for our previous work. Applying a high-level synthesis (HLS) design methodology for Xilinx FPGA, the implementation results of logic count with 10,677 LUTs, 3,714FFs and 66 DSPs is obtained. The implemented video encoder achieves less than 1.0 µs low-latency and compression to 39.4% without significant visual degradation. As a result, cost effective ultra-low-latency video encoder is implemented for low cost FPGA.

This paper describes a scalable architecture for high-resolution real-time optical flow processor and the design for 60-fps real-time Full-HD system. A previously proposed 30-fps WXGA real-time processor is re-designed as an IP (WXGA-IP) for the proposed Full-HD processor, which adopts a scalable multiprocessor structure. In addition, three methods are newly proposed, namely an improved hierarchical method, an improved initial value creation method, which reduces the number of iterative computations, and an adaptive acceleration parameter selection method that uses the built-in CPU. The realtime processing of 60-fps Full-HD video, which requires four times the processing power of WXGA video, is realized using twice the hardware while maintaining flow detection accuracy at a similar operating frequency compared to those of WXGA-IP.

We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high- k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent high-speed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros.

An autonomous mobile robot in a human living space should be able to not only realize collision-free motion but also give way to humans depending on the situation. Although various reactive obstacle avoidance methods have been proposed, it is difficult to achieve such motion. On the other hand, 3D X-Y-T space path planning, which takes into account the motion of both the robot and the human in a look-ahead time horizon, is effective. This paper proposes a real-time obstacle avoidance method for an autonomous mobile robot that considers the robots dynamic constraints, the personal space, and human directional area based on grid-based 3D X-Y-T space path planning. The proposed method generates collision-free motion in which the robot can yield to humans. To verify the effectiveness of the proposed method, various experiments in which the humans position and velocity were estimated using laser range finders were carried out.

A 100-MHz 51.2-Gb/s packet lookup engine LSI for packet inspection was proposed in a previous paper. High throughput and low power consumption was realized by introducing a combined mismatch detection circuit and linked-list hash table, minimizing the amount of memory accesses. The LSI has an automatic table update function. In this paper, this automatic rule registration and deletion function on the packet lookup engine LSI is described, meaning various tables included in the circuits, that is, the Mismatch Table, Index Table, and Rule Table are automatically configured by only inputting rules to be registered or deleted using embedded hardware on the LSI. This function utilizes a match and mismatch assessment for normal packet inspection operations.

An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is chosen in order to make the access transistor operate in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The WNM shift amount is determined from the measured WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. Together with the maximum likelihood method, a normal distribution of the AWNM drastically improves development efficiency because the write failure probability can be estimated from a small number of samples. The effectiveness of the proposed method is verified using the Monte Carlo simulation.

We propose an optical flow processor, which allows real-Time processing of WXGA 30-fps at 178.3 MHz. By introducing the SOR method and a pipeline operation for the Gauss-Seidel method to the iterative flow calculation, computational complexity can be reduced to 14.5% when compared to the previous HOE processor. We decreased the area of the embedded memory by using the image division method, applying line memory, and optimizing the computation word length. The core size of the designed processor is 16.82 mm2 in 90 nm process technology, which is approximately 5% of the previous HOE processor. The processor can operate completely in parallel, which ensures high-resolution scalability. © 2015 IEEE., 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015; Belgrade; Serbia; 22 April 2015 through 24 April 2015; Category numberE5519; Code 116884

A Field Programmable Sequencer and Memory (FPSM), which is an embedded memory based programmable device for peripherals on micro controller units, has been proposed at the architecture level. The FPSM functions not only as the memory but also as finite autonomous state transition controls independent of the CPU. In this paper, implementation on the LSI is described. The FPSM, fabricated using 180-nm 1-poly and 5-metal CMOS process technology, operates at the maximum frequency of 61.5 MHz with a power supply voltage of 1.8 V. The power consumption is 1.0 mW per programmable unit at the target frequency of 50 MHz. The performance of fundamental peripherals such as timers, shifters, serial receivers/transmitters, FIFOs and Pulse Width Modulations (PWM) are evaluated and verified.

This paper presents a real-time collision avoidance method with simultaneous control of both translational and rotational motion with consideration of a robot width for an autonomous omni-directional mobile robot. In the method, to take into consideration the robot’s size, a wide robot is regarded as a capsule-shaped case not a circle. With the proposed method, the wide robot can decide the direction of translational motion to avoid obstacles safely. In addition, the robot can decide the direction of the rotational motion in real time according to the situation to perform smooth motion. As an example of design method of the proposed method, novel control method based on the fuzzy potential method is proposed. To verify its effectiveness, several experiments using a real robot are carried out.

This paper presents a real time collision avoidance method for an autonomous omnidirectional mobile robot considering shape of the robot and movable area by heights based on simultaneous control of translational and rotational motion. Service robots which have been developed in recent years have arms to work and execute tasks. In these robots, the size of width is sometimes not equal to that of depth by heights. In order to avoid obstacles considering safety and mobility for the robots, it is necessary to evaluate shape of the robot and movable area by heights. To evaluate them, the robot model is defined by heights. Evaluating of the robot model and the movable area for each height, if the robot is unable to move keeping a safe distance from the obstacles, the robot determines the suitable orientation angle considering the minimum length from the center of the robot model to that outer shape. In this paper, the novel control method based on the fuzzy potential method is presented. To verify the effectiveness of the proposed method, several numerical simulations are carried out.

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0- mu m CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment. >

A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538 k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0- mu m double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode. >

A wide range motion estimation with exhaustive search is the best approach for high quality encoding applications. To perform the required computational power, a 165 GOPS (giga operations per second) exhaustive motion estimation processor ME3 has been developed. The ME3 is powerful enough to realize a range of -64/+63 pixels horizontally and -32/+31 pixels vertically with a single chip. A dual-array architecture supports not only high calculation power but also luminance and chrominance based search to increase picture quality. Also, the ME3 outputs extra vectors as candidates to enhance the picture quality. Using a multi-chip configuration, the exhaustive search range can be easily expanded to meet the requirements of MP@HL encoder. It is implemented using 0.35 /spl mu/m CMOS technology and contains 1.9 million transistors in an area of 8.5/spl times/8.5 mm/sup 2/.

This paper describes a chip set architecture for a programmable video encoder based on the MPEG2 main profile at main level (MP@ML). The chip set consists of a Controller-LSI (C-LSI), a macroblock level Pixel Processor-LSI (P-LSI) and a Motion Estimation-LSI (ME-LSI). The chip set combined with synchronous DRAMs (SDRAM) supports the whole layer processing including rate-control and realizes the real-time encoding for ITU-R-601 resolution video (720/spl times/480 pixels at 30 frame/s) with glueless logic. The exhaustive motion estimation capability is scalable up to +-63.5/+-15.5 in the horizontal/vertical directions. This chip set solution can realize a low cost MPEG2 video encoder system with excellent video quality on a small PC card.

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.

Germinated barley foodstuff (GBF) contains insoluble protein and dietary fiber, and has the potential to attenuate diarrhea and colonic mucosal damage in colitis. Since GBF contains a poorly digested protein fraction, this protein may be transferred to and absorbed in the colon. It may therefore be possible to detect the GBF antigen in colitis patients with dysfunctional colonic mucosal barrier defense. In this study, the antigenic potency of GBF was examined in vivo and in vitro. Using the AOAC method, the indigestible fraction of GBF (dietary fiber) was obtained, and the poorly digested protein fraction in GBF was determined. Using Sprague Dawley rats with chronic colitis induced by dextran sulfate sodium (DSS, 2.5% in diet), a GBF and control diet were administered, and total and specific serum immunoglobulin E (IgE) against intestinal contents and the soluble GBF protein were determined. In addition, reactivity between serum and intestinal content were examined by gel electrophoresis mobility shift assay (EMSA). GBF showed relatively low protein digestibility (47%) because of its low solubility in neutral pH. Total serum IgE in both dietary groups was not significantly different, and specific IgE antibodies against intestinal contents and the soluble GBF protein were not significantly different. In addition, supershifts were not observed in either dietary group by EMSA. The possible antigenicity of oral GBF was considered to be low in this colitis model.

Background Avoiding a fall requires fast and appropriate step responses, stepping speed as a fall risk indicator has only been assessed in older adults. We have developed a new measurement system that applies a laser range finder to assess temporal and spatial parameters of stepping performance such as step speed, length, and accuracy. This measurement system has higher portability, lower cost, and can analyze a larger number of temporal and spatial parameters than existing measurement systems. The aim of this study was to quantify the system for measuring reaction time and stride duration by compared to that obtained using a force platform. Methods Ten healthy young adults performed steps in response to visual cues. The measurement system applied a laser range finder to measure the position and velocity of the center of each leg and of both legs. We applied the developed measurement system to the rhythmic stepping exercise and measured reaction time and stride duration. In addition, the foot-off time and foot-contact time were quantified using the measurement system, and compared to the foot-off time and foot-contact time quantified using a force platform. Results We confirmed that the measurement system can detect where a participant stood and measured reaction time and stride duration. Remarkable consistency was observed in the test-retest reliability of the foot-off time and foot-contact time quantified by the measurement system (p r = 0.997, stride duration: r = 0.879; p Conclusions The new measurement system provided a valid measure of temporal step parameters in young healthy adults. The validity of the system to measure reaction time and stride duration was evaluated, and confirmed by applying to the rhythmic stepping exercise.