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1. A Pragmatic Model to Predict Future Device Aging

2. Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs

3. Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis

4. Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET

5. Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts.

7. Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.

11. Towards high performance sub-10nm finW bulk FinFET technology.

16. Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

17. ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S/D Epitaxy

18. Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

19. Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

20. Vₜ Extraction Methodologies Influence Process Induced Vₜ Variability: Does This Fact Still Hold for Advanced Technology Nodes?

21. Combining TCAD and advanced metrology techniques to support device integration towards N3

24. Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies

25. Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies

26. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

27. First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

28. Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET

29. Process-induced $V_{t}$ variability in nanoscale FinFETs: Does $V_{t}$ extraction methods have any impact?

30. Variability sources in nanoscale bulk FinFETs and TiTaN- a promising low variability WFM for 7/5nm CMOS nodes

31. The Improvement of Subthreshold Slope and Transconductance of p-Type Bulk Si Field-Effect Transistors by Solid-Source Doping

32. Transient Overshoot of Sub-10nm Bulk FinFET ESD Diodes with S/D Epitaxy Stressor

33. Effect of Sub-10nm Fin-widths on the Analog Performance of FinFETs

34. CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies

35. Impact of 1μ m TSV via-last integration on electrical performance of advanced FinFET devices

36. Towards optimal ESD diodes in next generation bulk FinFET and GAA NW technology nodes

37. On the ballistic ratio in 14nm-Node FinFETs

38. Efficient physical defect model applied to PBTI in high-κ stacks

39. Statistical characterization and modeling of drain current local and global variability in 14 nm bulk FinFETs

40. Fast Ramped Voltage Characterization of Single Trap Bias and Temperature Impact on Time-Dependent <tex-math notation='TeX'>\(V_{\rm TH}\) </tex-math> Variability

41. Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?

42. Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$-FinFETs

43. Extraction of the Random Component of Time-Dependent Variability Using Matched Pairs

44. Sidewall Crystalline Orientation Effect of Post-treatments for a Replacement Metal Gate Bulk Fin Field Effect Transistor

45. Charge based DC compact modeling of bulk FinFET transistor

46. Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations

47. Towards high performance sub-10nm finW bulk FinFET technology

48. Complete extraction of defect bands responsible for instabilities in n and pFinFETs

49. A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs

50. Scalpel soft retrace scanning spreading resistance microscopy for 3D-carrier profiling in sub-10nm WFIN FinFET

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