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In this study, we fabricated an n- type fin field-effect transistor (FinFET) and a p- type FinFET (p-FinFET) to compare their hot carrier degradation (HCD) in 14-nm technology nodes. We analyzed the HCD under different gate voltages ( $\text{V}_{\text {G}}$ ) and found that in a 14-nm technology node, the HCD of the p- FinFET was more serious than that of the n- type FinFET (n-FinFET). In addition, as $\text{V}_{\text {G}}$ increased, the HCD mechanism of the p- FinFET changed from electron–electron scattering (EES) to multiple-vibration excitation (MVE) faster than that of the n- FinFET did; thus, a larger threshold voltage ( $\text{V}_{\text {T}}$ ) shift was observed for the n- FinFET. When $\text{V}_{\text {G}}$ increased to $\text{V}_{\text {T}}+1.2$ V for the n- FinFET and to $\text{V}_{\text {T}} -{0.8}$ V for the p- FinFET, $\Delta \text{V}_{\text {T}}$ began to increase rapidly under hot carrier stress. The distributions of $\tau \times {(}\frac {I_{B}}{I_{D}}{)}^{-{2.7}}$ - ${I}_{D}$ for the n- FinFET and p- FinFET used in this study indicated that the mechanism of HCD changed from EES to MVE as $\text{V}_{\text {G}}$ increased. This result suggests that the p- FinFET experienced more serious HCD than did the n- FinFET because of the dominance of MVE in the p- FinFET. The HCD mechanism changed with a lower $\text{V}_{\text {G}}$ value for the p- FinFET than for the n- FinFET. Finally, HCD occurred more uniformly in the entire channel for the p- FinFET than for the n- FinFET.

This work investigates a low-temperature and high-pressure (LTHP) hydrogen treatment in Si-channel and SiGe-channel metal–oxide–semiconductor capacitors (MOSCAPs). The LTHP hydrogen treatment can repair dangling bonds in the SiO2/Si and SiO2/SiGe interfaces to enhance device performance. Additional parameters of the treatment, including treatment pressure and time, are also investigated to better understand the reaction mechanisms, which further proves the effectiveness and potential of this supercritical fluid (SCF)-based treatment. In addition, this treatment will not damage the front structure and materials due to the relatively low process temperature (120 °C). Therefore, this treatment can be a nondestructive postannealing process. The results of extracting interface defect density ( ${D}_{{\text {it}}}{)}$ by the conductance method show that there is an ~51% reduction in the defect density after this posttreatment, a significant decrease. Finally, a TCAD simulation of different defect densities verifies the repair mechanism of deep-level defects.

Fast recovery diodes (FRD) are widely used in transformer circuits for fast switching. Generally, in order to reduce forward voltage to achieve fast switching, the doping concentration is increased to reduce on-state resistance (Ron). This, however, will also increase reverse bias leakage as well as recovery time, resulting in a large amount of excess power consumption. In this letter, we use a unique low temperature supercritical fluid treatment process (LTSCF) to reduce this reverse bias leakage current, without affecting the on-state characteristics or switching characteristics. Experimental results show that the device’s average reverse bias leakage was reduced by 65% after LTSCF.

This work investigates the effects of HfO2 layer defects, formed by the Al atoms in the metal gate, on performance and reliability in advanced n-type metal–oxide–semiconductor field-effect transistors (n-MOSFETs) with different Al content in the gate stacks. Many groups have proposed theories (e.g., Si–H bond dissociation, trapped in high- ${k}$ defects and impact ionization) to explain the degradation mechanisms in MOSFETs, with most focusing on the dissociation of the Si-H bond at the Si/SiO2 interface and the carrier trapping in the high- $k$ layer. However, for multi- ${V}_{{\text {th}}}$ devices, experimental results indicate that the formation of defects by Al atoms in the HfO2 layer is the main reason for degradation in advanced n-MOSFETs. Therefore, we propose a mechanism to clarify the deterioration in advanced n-MOSFETs with different Al content in the gate stacks, and this mechanism is confirmed by positive bias temperature instability (PBTI), hot carrier instability (HCI), HCI power-law fitting and the gate-induced drain leakage (GIDL) measurement.

This work performs fundamental electrical measurements and a positive bias temperature instability (PBTI) test on an N-type metal oxide semiconductor capacitor (MOSCAP) and a La2O3 dipole-doped N-type MOSCAP. Experimental results show that the dipole-doped N-type MOSCAP has a lower threshold voltage and gate current leakage than do the N-type MOSCAP. After positive bias stress, an abnormal gate current leakage decrease appears in both dipole-doped and normal N-type MOSCAPs under short term stress. Analysis of capacitance and gate current measurements indicate that electron trapping and defect generation cause the change in gate current after positive bias stress. Generally, devices with higher gate leakage have more severe degradation after PBTI. However, in this work, the dipole sample shows a lower initial gate current leakage but higher gate current degradation than those found in the control sample after PBTI. Based on the electrical measurement results and the energy band simulation, a conduction model was proposed to explain the abnormal PBTI of the dipole-doped N-type MOSCAP.

In this study, the mechanism of the kink effect observed during the switching operation in AlGaN/GaN high-electron-mobility transistors is thoroughly analyzed. The I D–V G characteristics show a drop in I D and a positive shift in threshold voltage (V T) when the kink effect occurs. Then, using Silvaco software to simulate the trap position, the negative buffer trap induces the V T to shift positively, dominating the decrease in the I D. By using a long-term DC stress test under bias conditions, where the kink phenomenon occurred, the V T will shift in the negative direction, which shows that the hole generated by impact ionization (II) plays a key role in the kink effect. Furthermore, the I D–V G after kink-effect stress does not respond to red, green or blue light illumination but does to UV light, which means that electron de-trapping cannot restore the V T shift caused by the kink effect. Finally, the complete mechanism of the kink effect is provided. The recombination of hot holes generated by II with the electron trapped in buffer defects is the main mechanism for the kink phenomenon.

This study investigates the recovery behavior of GaN high-electron mobility transistors on SiC substrates under different hot-carrier stress conditions. The threshold voltage shifts positively due to hot electron trapping at the buffer layer under hot-carrier stress. However, the recovery between semi-on (Vt < VG < 0 V) hot-carrier stress and on-state (VG > 0 V) carrier stress is significantly different. This phenomenon is systematically discussed in terms of the applied gate voltage under stress condition, which affects the occupation of the surface donor states. After applying a semi-on hot-carrier stress, the threshold voltage continues to shift positively after relaxing the applied voltage. In contrast, the threshold voltage exponentially recovers after applying an on-state hot-carrier stress. Silvaco technology computer aided design (TCAD) simulation was performed to verify the effect of the surface donor state on the threshold voltages. Since switching between on-state and off-state in RF-applications includes both conditions, we suggest that the surface donor states are crucial to determine the failure of devices.

This work demonstrates a modified conductance method for the characterization of interface traps in gallium-nitride metal-insulator-semiconductor high electron mobility transistors. It is observed that the defect states cannot be extracted by conventional conductance method in which the capacitance of insulator layer, for instance silicon nitride, is typically selected as the oxide capacitance for conductance calculation. Although the origin remains unclear, it is likely due to the additional effect from aluminum gallium nitride blocking layer that significantly affects the extraction results. A modified equivalent circuit model is proposed accordingly to solve this issue. Additionally, temperature-dependent measurement is carried out to probe the interface traps under different energy levels by our proposed technique.

This study investigates the impact of fin profiles under hot carrier stress, which defines different base widths: wide-base samples with the smallest slope, medium-base samples, and narrow-base samples with a larger slope. The performance of the narrow samples is better than the medium samples, regardless of transconductance, on-state current, subthreshold swing or drain-induced barrier lowering, demonstrating that the narrow profile samples’ mobility and gate control are better. In long channel devices, the trend of hot carrier degradation (HCD) is in agreement with previous references, and is dependent on the transverse electric field and the fin shapes. However, this trend does not exist for short-channel devices. Positive bias stress and technology computer aided design simulation are applied for investigation and to clarify the reasons for this abnormal HCD trend. Finally, by fitting the multiple vibrational excitation (MVE) mechanism, the slope of the trend lines in the short channel devices are found to indeed match the bending mode. In other words, the disappearance of the general trend between the HCD and fin profiles is caused by the change in the mechanism in the short-channel device. Because the MVE mechanism is independent from the electric field, the narrow profile fin shape more effectively promotes gate control and better performance without affecting the reliability in short channel devices. These results can provide a clear direction for fin shape designers in the future.

In this work, a two-step degradation phenomenon in D-mode Si3N4/AlGaN/GaN metal–insulator–semiconductor-high electron mobility transistors is discussed systematically. During off-state stress, threshold voltage shifts positively for a short duration, and is followed by a negative shift. In contrast, the off-state leakage continues to decrease throughout the entire stress. Results of varied measurement conditions indicate that carrier trapping at different regions dominates this phenomenon. It is interesting that under a large lateral electric field, electron–hole pairs are generated and will then be trapped at the gate dielectric layer. Furthermore, when increasing the stress temperature, impact ionization due to carriers from the gate electrode becomes more severe. Finally, devices with different gate insulator thicknesses are performed to verify the physical model of the degradation behavior.

In this research, based on I–V and C–V measurement at different temperatures, the interface defect density in the device with the Si/SiGe channel was discussed. In addition, negative bias temperature instability (NBTI) is also studied. In previous research, most of the flat-band voltage (V FB) shifts during NBTI stress was attributed to hole injection. In this article, however, the release of atomic hydrogen from the Si–H bonds at the SiO2/Si interface and at the SiGe interface produces a fixed oxide charge, which causes V FB shifts which vary with material.

In this work, low-temperature (100 °C–200 °C) and high-pressure (LTHP) nitridation treatment was applied to improve the performance and reliability of dipole-doped metal oxide semiconductor capacitor. After the LTHP nitridation, the gate leakage and the capacitance of the dipole sample demonstrated obvious enhancements. Furthermore, the degradation of positive bias stress (PBS) and time dependent dielectric breakdown on these LTHP-treated devices apparently decrease. The LTHP was confirmed to effectively enhance the performance and the endurance of the dipole sample. Finally, the mechanism of LTHP nitridation treatment was established to explain the improvements in dipole samples.

This work investigates the effect of process temperature on one-transistor-one-capacitor ferroelectric random access memory (1T1C FeRAM) cells fabricated with a HfZrOx ultrathin film applied as the 1T1C capacitor. Traditionally, the capacitor in 1T1C devices is grown on the drain, and such a structure is a type of dynamic memory. Such a structure, however, is prone to the leakage current phenomenon, which causes the amount of charge stored in the capacitor to be insufficient, leading to inaccurate data reading. To solve this problem, an alternative 1T1C structure placing the capacitor on the gate terminal has been proposed. For these alternative 1T1C FeRAM devices, our experimental results indicate that the deposition temperature of the ferroelectric layer has a significant effect on the basic electrical properties. To clarify this phenomenon, we propose a physical model which is based on the effect of the deposition temperature on the HfZrOx grain size.