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\Al2\O3 high- \kappa stack is a strong candidate as the dielectric layer in Flash memory cells for technology generations beyond sub-20 nm. In this paper, the cause of abnormal VTH/VFB shift at low operating electric fields is investigated, i.e., VTH/VFB reduces at low positive gate biases and increases at low negative gate biases. It is found that this instability does not originate from the electrons trapping/detrapping from the gate nor from the dielectric relaxation. For the first time, extensive experimental evidences show that this shift is caused by as-grown mobile charges in \Al2\O3 layers generated by postdeposition annealing at 1000 ^\circ\C or above. Its impacts on program/erase windows and read/pass disturbance in Flash memory cells are also evaluated. [ABSTRACT FROM PUBLISHER]

A fast response technique is developed to investigate the short-term postprogram and post-erase discharge in Flash memory devices. The procedure is based on fast VTH -evaluation methods developed for bias temperature instability and provides the transient characteristics after 20 ms under the program or erase conditions. The following different structures are investigated: 1) \SiO2/high-k stacks; 2) charge trap memories; 3) and floating gate memories. Dielectrics targeted for Flash memory applications are used as charge trap layers and interpoly dielectrics. In this paper, we show results on \Al2\O3, DyScO, GdScO, and hexagonal and perovskite LuAlO. The postprogram and post-erase curves hold useful information about the dielectric properties and are used as a fast screening technique for alternative materials. [ABSTRACT FROM PUBLISHER]

The operation and reliability of nonvolatile memory concepts based on charge storage in nitride layers, such as TANOS (\TaN/Al2\O3/\Si3\N4/ \SiO2/\Si), require detailed information on the energy and spatial distribution of the charge defects in both the nitride and the \Al2\O3 blocking dielectric. This paper focuses on the characterization of \Al2\O3. We have successfully applied complementary trap characterization techniques to crystalline \gamma-phase- \Al2\O3 in order to obtain a complete picture of the spatial and energetic distribution of the defect density. As a result, two defect types at energy levels 1.8 and 3.5 eV below the conduction band edge are found. [ABSTRACT FROM PUBLISHER]

We present an experimental methodology that demonstrates the suitability of the conventional three-lumped-parameter model for gate impedance of MOSFET devices at frequencies from dc to the gigahertz range, which permits accurate' extraction of model parameters. The parasitic effects at a high frequency are minimized by using radio frequency techniques (i.e., short return paths and de-embedding structures), whereas a robust parameter extraction algorithm overcomes possible instrument inaccuracies. When combined, these allow simultaneous extraction of all three parameters (i.e., Cgate, RDT, and Rseries) from the model. The technique is applied to conventional SiO2-based MOSFET devices and to ultraleaky HfO2 devices with aggressively scaled gate dielectric thickness. [ABSTRACT FROM AUTHOR]